# Analog Design with Discrete Components

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This chapter is from the book

## 3.10 Framework for TTL/CMOS Logic

Before we enter the digital realm and leave the world of analog electronics behind (for the most part), I thought it would be fun and very relevant to show examples of how transistors are used to create digital logic gates. Of course, you may have no idea what a digital logic gate is, but briefly, a logic gate is a hardware implementation of the standard logic functions you use when programming. For example:

Bitwise NOT Logic

• z = ~y

This assigns x the bit inverted value of y.

Bitwise AND Logic

• z = x & y

This assigns z the bitwise AND of x and y.

Bitwise OR Logic

• z = x | y

This assigns z the bitwise OR of x and y.

Of course the "logical" NOT, AND, and OR are somewhat different and deal with entire numbers; however, at the bit level, logical operations and bitwise are identical. With this in mind, if we are dealing with Boolean values only then can we map our computer code directly to hardware and make assignments like

• BOOL x,y,z;
• z = ~(x & y | z);

So the question is, how to implement this in hardware? There are lots of ways to do this; of course the way we will do this in the next chapter is with ICs that implement logic functions. But, for now, let’s see if we can go through the same thought process the IC designers did and build some simple logic gates from transistors and resistors that implement these logic functions or variations thereof. This way you can see the transition from analog to digital better, but still realize that under all the digital electronics are always analog components—always.

### 3.10.1 Creating a Convention

The first thing we need to agree on for our little model experiment is a set of conventions; that is, what means what in relation to voltages? We are going to loosely model our gates after the most popular logic system in the world, TTL (transistor transistor logic), which refers to both a method of implementation and a set of voltages and currents. We are not so much interested in actual implementation of TTL since we are just trying to make something that is semi-compatible. So we need to know two things:

1. What is the voltage level representation for a logic "0"?
2. What is the voltage level representation of a logic "1"?

If you take a look at Figure 3.66 you will see a graph that shows the logic levels for a number of different logic families (courtesy of TI). We are only interested in the TTL family for now, since it’s easiest to model. Referring to the TTL switching standard there are a number of demarcations on the graph; their meanings are as follows:

• VCC/GND—These are the "rails" of the power supply. VCC is the +5 supply and ground is 0V.
• Vol—Voltage output low. This is the highest voltage a TTL gate will give when output a low.
• Vil—Voltage input low. This is the highest voltage a TTL gate will detect as a low input.
• Vih—Voltage input high. This is the lowest voltage a TTL gate will detect as a high input.
• Voh—Voltage output high. This is the lowest voltage a TTL gate is guaranteed to output a high at.

These seems a little weird, but the bottom line is that we need to consider two things: what a TTL gate guarantees as low and high when it is an output, and what a TTL gate will detect as a low and high as an input. Between the text and the figure you should be able to get it. Finally, the last assumption is that the digital systems use +5V and that a high or "1" is +5 and a low or "0" is 0V ideally. With that in mind, we need to design our model "TTL" gates with those constraints or at least close.

#### 3.10.1.1 Building an Inverter

The inverter is the basis on 99% of all digital logic; if you can invert a signal then you can usually derive everything from there, so we will start with an inverter. Figure 3.67 depicts one possible design. The circuit operation is as follows. If we apply a 0V to the base at input X (Vin) then the transistor is OFF; in this case, there is no base current and thus no collector current (other than a very small leakage current), therefore the output Z (Vout) will output nearly 5V. Thus, an input of 0V (logic 0) outputs a 5V (logic 1). So far so good.

Now, the hard part. Let’s apply a 5V (logic 1) to the base at X (Vin); when we do this we turn ON the transistor and it starts conducting. When it does so the base-emitter junction wants to have a 0.6V drop across it; therefore, the base will be at

• VB = VE + 0.6V

and since VE is at ground, VB = 0.6V. Therefore, we can compute IB as the voltage drop over Rin divided by the resistance of Rin:

• IB = (5V – 0.6V)/1KΩ = 4.4mA

We know that IC = hFE*IB roughly, and assuming an hFE of 100, we get an IC of

• IC = 100*4.4mA = 44mA

However, this is only tentative; it may be less if this current violates one of the transistor rules. Let’s see. With a collector current of 44mA, that means that the voltage drop over Rout is

• Vrout = 44mA*100Ω = 4.4V

Thus, the voltage at the collector VC and the output Z (Vout) is (5V-4.4V)=0.6V, which is above the requirement of 0.2V worst case for the collector above ground. Therefore, when we apply a signal of 5V (logic 1), we get a 0.6V output roughly (logic 0), and thus we have an inverter. Table 3.1 lists the inputs and outputs, so you can confirm everything at once and assure yourself we have an inverter.

#### Table 3.1 Logic/Response Table for the "Model" TTL Inverter

 Input Ouput X (Vin) Z (Vout) 0 (0V) 1 (5.0V) 1 (5V) 0 (0.6V)

It’s almost perfect! And in reality, the output low will tend to be lower. Of course, we haven’t tested against the Vil, Vih values to see if we match the tolerance on those constraints, but that’s not important. We at least have a TTL inverter that given solid inputs outputs TTL outputs.

#### 3.10.1.2 Building a NAND Gate

So a single transistor can be used as an inverter. We can use this fact and the design now as a block and create other gates. Let’s create a NAND gate. Of course we could create an AND gate, but then we would have to invert its output, so a NAND is a little easier to implement.

Since we have the analysis of the inverter under our belt, we can analyze the NAND gate without so much detail. Referring to Figure 3.68, there are two inverters more or less placed in series. The operation is as follows: When either input X,Y or both are at 0V then one or both of the transistors are OFF. Therefore, there is no appreciable collector current and the output Z will hang at approximately 5.0V, a bit less; remember there is still a bit of leakage current even when the transistor(s) are OFF. Thus, a logic 0,0 or 0,1, or 1,0 all result in an output of a logic 1 at nearly 5.0V. This is looking like a NAND so far. The last case is when we turn both transistors on with logic 1’s at X and Y. In this case, we turn both transistors on and then conduct hard; the collector voltages will each be 0.2V above the respective emitter’s for a worst case of 0.4V above ground at the final output node Z (Vout). So to reiterate when both inputs are driven to logic 1 (5V), the output goes to 0.4V or so, a logic 0.

Let’s take these results and build another logic/response truth table as shown in Table 3.2.

#### Table 3.2 The Logic/Response Truth Table for the 2-input NAND Gate

 Input Input Output X (Vin1) Y (Vin2) Z (Vout) 0 (0V) 0 (0V) 1 (5.0V) 0 (0V) 1 (5V) 1 (5.0V) 1 (5V) 0 (0V) 1 (5.0V) 1 (5V) 1 (5V) 0 (0.4V)

Reviewing the truth table, the circuit is indeed a NAND gate. Of course, if you wanted to, you could attach an inverter to the output at Z and then invert the NAND to create an AND gate.

#### 3.10.1.3 Building a NOR Gate

Finally, let’s make a NOR gate. Again we will use the inverter as our basis. Figure 3.69 shows the final 2-input NOR design; basically we simply put two inverters in parallel. Operation of the NOR is similar to the NAND. If both inputs are held at a logic 0 then neither transistor conducts and the output at Z is nearly 5V, or a logic 1. If either transistor is turned on with a logic 1 then the collector circuit of the transistor conducts hard; the other transistor is a high impedance load in parallel with the low impedance conducting transistor and can thus be disregarded. Therefore, with either or both transistors conducting, the collector circuit of one or both of the transistors will have a lot of current flowing and the voltage will drop over the output resistor Rout resulting in a near 0V at the output Z (Vout). Transcribing this behavior to Table 3.3, we see we indeed have a NOR gate!

#### Table 3.3 The Logic/Response Truth Table for the 2-input NOR Gate

 Input Input Output X (Vin1) Y (Vin2) Z (Vout) 0 (0V) 0 (0V) 1 (5.0V) 0 (0V) 1 (5V) 0 (5.0V) 1 (5V) 0 (0V) 0 (5.0V) 1 (5V) 1 (5V) 0 (0.4V)

This concludes our analysis of the basic implementation of gates with a TTL-like model using transistors and resistors. Now, in the next chapter when we discuss output voltages, currents, etc. you will have a foundation and know where these things come from; they are the underlying analog parts that have been abstracted away, but they are always there nonetheless.