# Analog Design with Discrete Components

This chapter is from the book

## 3.10 Framework for TTL/CMOS Logic

Before we enter the digital realm and leave the world of analog electronics behind (for the most part), I thought it would be fun and very relevant to show examples of how transistors are used to create digital logic gates. Of course, you may have no idea what a digital logic gate is, but briefly, a logic gate is a hardware implementation of the standard logic functions you use when programming. For example:

Bitwise NOT Logic

• z = ~y

This assigns x the bit inverted value of y.

Bitwise AND Logic

• z = x & y

This assigns z the bitwise AND of x and y.

Bitwise OR Logic

• z = x | y

This assigns z the bitwise OR of x and y.

Of course the "logical" NOT, AND, and OR are somewhat different and deal with entire numbers; however, at the bit level, logical operations and bitwise are identical. With this in mind, if we are dealing with Boolean values only then can we map our computer code directly to hardware and make assignments like

• BOOL x,y,z;
• z = ~(x & y | z);

So the question is, how to implement this in hardware? There are lots of ways to do this; of course the way we will do this in the next chapter is with ICs that implement logic functions. But, for now, let’s see if we can go through the same thought process the IC designers did and build some simple logic gates from transistors and resistors that implement these logic functions or variations thereof. This way you can see the transition from analog to digital better, but still realize that under all the digital electronics are always analog components—always.

### 3.10.1 Creating a Convention

The first thing we need to agree on for our little model experiment is a set of conventions; that is, what means what in relation to voltages? We are going to loosely model our gates after the most popular logic system in the world, TTL (transistor transistor logic), which refers to both a method of implementation and a set of voltages and currents. We are not so much interested in actual implementation of TTL since we are just trying to make something that is semi-compatible. So we need to know two things:

1. What is the voltage level representation for a logic "0"?
2. What is the voltage level representation of a logic "1"?

If you take a look at Figure 3.66 you will see a graph that shows the logic levels for a number of different logic families (courtesy of TI). We are only interested in the TTL family for now, since it’s easiest to model. Referring to the TTL switching standard there are a number of demarcations on the graph; their meanings are as follows:

• VCC/GND—These are the "rails" of the power supply. VCC is the +5 supply and ground is 0V.
• Vol—Voltage output low. This is the highest voltage a TTL gate will give when output a low.
• Vil—Voltage input low. This is the highest voltage a TTL gate will detect as a low input.
• Vih—Voltage input high. This is the lowest voltage a TTL gate will detect as a high input.
• Voh—Voltage output high. This is the lowest voltage a TTL gate is guaranteed to output a high at.

These seems a little weird, but the bottom line is that we need to consider two things: what a TTL gate guarantees as low and high when it is an output, and what a TTL gate will detect as a low and high as an input. Between the text and the figure you should be able to get it. Finally, the last assumption is that the digital systems use +5V and that a high or "1" is +5 and a low or "0" is 0V ideally. With that in mind, we need to design our model "TTL" gates with those constraints or at least close.

#### 3.10.1.1 Building an Inverter

The inverter is the basis on 99% of all digital logic; if you can invert a signal then you can usually derive everything from there, so we will start with an inverter. Figure 3.67 depicts one possible design. The circuit operation is as follows. If we apply a 0V to the base at input X (Vin) then the transistor is OFF; in this case, there is no base current and thus no collector current (other than a very small leakage current), therefore the output Z (Vout) will output nearly 5V. Thus, an input of 0V (logic 0) outputs a 5V (logic 1). So far so good.

Now, the hard part. Let’s apply a 5V (logic 1) to the base at X (Vin); when we do this we turn ON the transistor and it starts conducting. When it does so the base-emitter junction wants to have a 0.6V drop across it; therefore, the base will be at

• VB = VE + 0.6V

and since VE is at ground, VB = 0.6V. Therefore, we can compute IB as the voltage drop over Rin divided by the resistance of Rin:

• IB = (5V – 0.6V)/1KΩ = 4.4mA

We know that IC = hFE*IB roughly, and assuming an hFE of 100, we get an IC of

• IC = 100*4.4mA = 44mA

However, this is only tentative; it may be less if this current violates one of the transistor rules. Let’s see. With a collector current of 44mA, that means that the voltage drop over Rout is

• Vrout = 44mA*100Ω = 4.4V

Thus, the voltage at the collector VC and the output Z (Vout) is (5V-4.4V)=0.6V, which is above the requirement of 0.2V worst case for the collector above ground. Therefore, when we apply a signal of 5V (logic 1), we get a 0.6V output roughly (logic 0), and thus we have an inverter. Table 3.1 lists the inputs and outputs, so you can confirm everything at once and assure yourself we have an inverter.

#### Table 3.1 Logic/Response Table for the "Model" TTL Inverter

 Input Ouput X (Vin) Z (Vout) 0 (0V) 1 (5.0V) 1 (5V) 0 (0.6V)

It’s almost perfect! And in reality, the output low will tend to be lower. Of course, we haven’t tested against the Vil, Vih values to see if we match the tolerance on those constraints, but that’s not important. We at least have a TTL inverter that given solid inputs outputs TTL outputs.

#### 3.10.1.2 Building a NAND Gate

So a single transistor can be used as an inverter. We can use this fact and the design now as a block and create other gates. Let’s create a NAND gate. Of course we could create an AND gate, but then we would have to invert its output, so a NAND is a little easier to implement.

Since we have the analysis of the inverter under our belt, we can analyze the NAND gate without so much detail. Referring to Figure 3.68, there are two inverters more or less placed in series. The operation is as follows: When either input X,Y or both are at 0V then one or both of the transistors are OFF. Therefore, there is no appreciable collector current and the output Z will hang at approximately 5.0V, a bit less; remember there is still a bit of leakage current even when the transistor(s) are OFF. Thus, a logic 0,0 or 0,1, or 1,0 all result in an output of a logic 1 at nearly 5.0V. This is looking like a NAND so far. The last case is when we turn both transistors on with logic 1’s at X and Y. In this case, we turn both transistors on and then conduct hard; the collector voltages will each be 0.2V above the respective emitter’s for a worst case of 0.4V above ground at the final output node Z (Vout). So to reiterate when both inputs are driven to logic 1 (5V), the output goes to 0.4V or so, a logic 0.

Let’s take these results and build another logic/response truth table as shown in Table 3.2.

#### Table 3.2 The Logic/Response Truth Table for the 2-input NAND Gate

 Input Input Output X (Vin1) Y (Vin2) Z (Vout) 0 (0V) 0 (0V) 1 (5.0V) 0 (0V) 1 (5V) 1 (5.0V) 1 (5V) 0 (0V) 1 (5.0V) 1 (5V) 1 (5V) 0 (0.4V)

Reviewing the truth table, the circuit is indeed a NAND gate. Of course, if you wanted to, you could attach an inverter to the output at Z and then invert the NAND to create an AND gate.

#### 3.10.1.3 Building a NOR Gate

Finally, let’s make a NOR gate. Again we will use the inverter as our basis. Figure 3.69 shows the final 2-input NOR design; basically we simply put two inverters in parallel. Operation of the NOR is similar to the NAND. If both inputs are held at a logic 0 then neither transistor conducts and the output at Z is nearly 5V, or a logic 1. If either transistor is turned on with a logic 1 then the collector circuit of the transistor conducts hard; the other transistor is a high impedance load in parallel with the low impedance conducting transistor and can thus be disregarded. Therefore, with either or both transistors conducting, the collector circuit of one or both of the transistors will have a lot of current flowing and the voltage will drop over the output resistor Rout resulting in a near 0V at the output Z (Vout). Transcribing this behavior to Table 3.3, we see we indeed have a NOR gate!

#### Table 3.3 The Logic/Response Truth Table for the 2-input NOR Gate

 Input Input Output X (Vin1) Y (Vin2) Z (Vout) 0 (0V) 0 (0V) 1 (5.0V) 0 (0V) 1 (5V) 0 (5.0V) 1 (5V) 0 (0V) 0 (5.0V) 1 (5V) 1 (5V) 0 (0.4V)

This concludes our analysis of the basic implementation of gates with a TTL-like model using transistors and resistors. Now, in the next chapter when we discuss output voltages, currents, etc. you will have a foundation and know where these things come from; they are the underlying analog parts that have been abstracted away, but they are always there nonetheless.

### InformIT Promotional Mailings & Special Offers

I would like to receive exclusive offers and hear about products from InformIT and its family of brands. I can unsubscribe at any time.

## Overview

Pearson Education, Inc., 221 River Street, Hoboken, New Jersey 07030, (Pearson) presents this site to provide information about products and services that can be purchased through this site.

This privacy notice provides an overview of our commitment to privacy and describes how we collect, protect, use and share personal information collected through this site. Please note that other Pearson websites and online products and services have their own separate privacy policies.

## Collection and Use of Information

To conduct business and deliver products and services, Pearson collects and uses personal information in several ways in connection with this site, including:

### Questions and Inquiries

For inquiries and questions, we collect the inquiry or question, together with name, contact details (email address, phone number and mailing address) and any other additional information voluntarily submitted to us through a Contact Us form or an email. We use this information to address the inquiry and respond to the question.

### Online Store

For orders and purchases placed through our online store on this site, we collect order details, name, institution name and address (if applicable), email address, phone number, shipping and billing addresses, credit/debit card information, shipping options and any instructions. We use this information to complete transactions, fulfill orders, communicate with individuals placing orders or visiting the online store, and for related purposes.

### Surveys

Pearson may offer opportunities to provide feedback or participate in surveys, including surveys evaluating Pearson products, services or sites. Participation is voluntary. Pearson collects information requested in the survey questions and uses the information to evaluate, support, maintain and improve products, services or sites, develop new products and services, conduct educational research and for other purposes specified in the survey.

### Contests and Drawings

Occasionally, we may sponsor a contest or drawing. Participation is optional. Pearson collects name, contact information and other information specified on the entry form for the contest or drawing to conduct the contest or drawing. Pearson may collect additional personal information from the winners of a contest or drawing in order to award the prize and for tax reporting purposes, as required by law.

If you have elected to receive email newsletters or promotional mailings and special offers but want to unsubscribe, simply email information@informit.com.

### Service Announcements

On rare occasions it is necessary to send out a strictly service related announcement. For instance, if our service is temporarily suspended for maintenance we might send users an email. Generally, users may not opt-out of these communications, though they can deactivate their account information. However, these communications are not promotional in nature.

### Customer Service

We communicate with users on a regular basis to provide requested services and in regard to issues relating to their account we reply via email or phone in accordance with the users' wishes when a user submits their information through our Contact Us form.

## Other Collection and Use of Information

### Application and System Logs

Pearson automatically collects log data to help ensure the delivery, availability and security of this site. Log data may include technical information about how a user or visitor connected to this site, such as browser type, type of computer/device, operating system, internet service provider and IP address. We use this information for support purposes and to monitor the health of the site, identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents and appropriately scale computing resources.

### Web Analytics

Pearson may use third party web trend analytical services, including Google Analytics, to collect visitor information, such as IP addresses, browser types, referring pages, pages visited and time spent on a particular site. While these analytical services collect and report information on an anonymous basis, they may use cookies to gather web trend information. The information gathered may enable Pearson (but not the third party web trend services) to link information with application and system log data. Pearson uses this information for system administration and to identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents, appropriately scale computing resources and otherwise support and deliver this site and its services.

This site uses cookies and similar technologies to personalize content, measure traffic patterns, control security, track use and access of information on this site, and provide interest-based messages and advertising. Users can manage and block the use of cookies through their browser. Disabling or blocking certain cookies may limit the functionality of this site.

### Do Not Track

This site currently does not respond to Do Not Track signals.

## Security

Pearson uses appropriate physical, administrative and technical security measures to protect personal information from unauthorized access, use and disclosure.

## Children

This site is not directed to children under the age of 13.

## Marketing

Pearson may send or direct marketing communications to users, provided that

• Pearson will not use personal information collected or processed as a K-12 school service provider for the purpose of directed or targeted advertising.
• Such marketing is consistent with applicable law and Pearson's legal obligations.
• Pearson will not knowingly direct or send marketing communications to an individual who has expressed a preference not to receive marketing.
• Where required by applicable law, express or implied consent to marketing exists and has not been withdrawn.

Pearson may provide personal information to a third party service provider on a restricted basis to provide marketing solely on behalf of Pearson or an affiliate or customer for whom Pearson is a service provider. Marketing preferences may be changed at any time.

## Correcting/Updating Personal Information

If a user's personally identifiable information changes (such as your postal address or email address), we provide a way to correct or update that user's personal data provided to us. This can be done on the Account page. If a user no longer desires our service and desires to delete his or her account, please contact us at customer-service@informit.com and we will process the deletion of a user's account.

## Choice/Opt-out

Users can always make an informed choice as to whether they should proceed with certain services offered by InformIT. If you choose to remove yourself from our mailing list(s) simply visit the following page and uncheck any communication you no longer want to receive: www.informit.com/u.aspx.

## Sale of Personal Information

Pearson does not rent or sell personal information in exchange for any payment of money.

While Pearson does not sell personal information, as defined in Nevada law, Nevada residents may email a request for no sale of their personal information to NevadaDesignatedRequest@pearson.com.

## Supplemental Privacy Statement for California Residents

California residents should read our Supplemental privacy statement for California residents in conjunction with this Privacy Notice. The Supplemental privacy statement for California residents explains Pearson's commitment to comply with California law and applies to personal information of California residents collected in connection with this site and the Services.

## Sharing and Disclosure

Pearson may disclose personal information, as follows:

• As required by law.
• With the consent of the individual (or their parent, if the individual is a minor)
• In response to a subpoena, court order or legal process, to the extent permitted or required by law
• To protect the security and safety of individuals, data, assets and systems, consistent with applicable law
• In connection the sale, joint venture or other transfer of some or all of its company or assets, subject to the provisions of this Privacy Notice
• To investigate or address actual or suspected fraud or other illegal activities
• To exercise its legal rights, including enforcement of the Terms of Use for this site or another contract
• To affiliated Pearson companies and other companies and organizations who perform work for Pearson and are obligated to protect the privacy of personal information consistent with this Privacy Notice
• To a school, organization, company or government agency, where Pearson collects or processes the personal information in a school setting or on behalf of such organization, company or government agency.

This web site contains links to other sites. Please be aware that we are not responsible for the privacy practices of such other sites. We encourage our users to be aware when they leave our site and to read the privacy statements of each and every web site that collects Personal Information. This privacy statement applies solely to information collected by this web site.