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Engineering the Power Delivery Network

This chapter describes digital electronic systems and gives a high-level overview of the Power Delivery Network (PDN) and signal network. It describes signal and power integrity effects on system performance and highlights power noise to signal coupling mechanisms. Finally, it addresses the need for concurrent SI/PI design methodology.

This chapter is from the book

1.1 What Is the Power Delivery Network (PDN) and Why Should I Care?

The power delivery network consists of all the interconnects in the power supply path from the voltage regulator modules (VRMs) to the circuits on the die. Generally, these include the power and ground planes in the boards, cables, connectors, and all the capacitors associated with the power supply. Figure 1.1 is an example of a typical computer board with multiple VRMs and paths delivering the power and ground to the pads of all the active devices.

Figure 1.1

Figure 1.1 A typical computer motherboard with multiple VRMs and active devices. The PDN includes all the interconnects from the pads of the VRMs to the circuits on the die.

The purpose of the PDN is to

  • Distribute low-noise DC voltage and power to the active devices doing all the work.

  • Provide a low-noise return path for all the signals.

  • Mitigate electromagnetic interference (EMI) problems without contributing to radiated emissions.

In this book, we focus on the first role of the PDN: to distribute a DC voltage and power to all the active devices requiring power and to keep the noise below an acceptable level. Unsuccessful noise control on the PDN will contribute to contraction of the eye of any signal. The amplitude of the eye in the vertical direction collapses from voltage noise. The time of the signal crossing a reference spreads out in the horizontal direction creating jitter and reduction of the eye opening. Internal core circuits might suffer setup and hold-time errors, leading to functional failures.

Depending on the circuit of the switching gates, the PDN noise will add to the signal coming from the transmitter (TX). This can also appear as noise on the voltage reference at the receiver (RX). In both cases, the PDN noise will reduce the noise margin available from other sources.

Figure 1.2 shows an example of the measured voltage noise between the core power and ground (Vdd and Vss) rails on a microprocessor die at three different on-die locations and two different voltage rails. In this example, the voltage noise is 125 mV. In many circuits, a large fraction of this voltage noise will appear superimposed on the signal at the RX.

Figure 1.2

Figure 1.2 Example of the noise between the Vdd and Vss rails in a microprocessor running at 300 MHz clock, measured at three different locations. More than 125 mV of noise is present.

Even if this noise by itself is not enough to cause a bit failure, it will contribute to eye closure, and with the other noise sources might result in a failure.

Voltage noise on the power rails of the chips also affects timing. The propagation delay, the time from which an input voltage transition propagates through the sequence of gates contributing to an output voltage transition, depends on the instantaneous voltage level between the In CMOS technology, the higher the drain-to-source voltage, the larger the electric fields in the channels and the shorter the propagation delay. Likewise, the lower the Vdd to Vss voltage, the longer the propagation delay.

This means that voltage noise on the Vdd to Vss rails on die directly contributes to timing variations in the output signals called jitter. A higher voltage on the Vdd rail “pulls in” a clock edge, whereas a lower rail voltage “pushes out” a clock edge. Figure 1.3 is an example of the measured jitter induced on a high-end FPGA test chip from voltage noise on the PDN.

Figure 1.3

Figure 1.3 Measured jitter on a clock signal in the presence of Vdd to Vss voltage noise.

In this example, a clock distribution net shares the Vdd rail with a number of other gates. These gates were switching with a pseudo-random bit sequence (PRBS), drawing large currents from the PDN and generating large transient voltage noise. This voltage noise, as applied to the clock distribution network gates, caused timing variations in the clock signal. The period jitter measurement, the period of time from one clock edge to the next clock edge, appears as the period of each clock. This measurement demonstrates the direct correlation between the voltage noise on the die and the jitter on the clock.

In this example, the sensitivity of the jitter from PDN noise is about 1 ps of jitter per mV of voltage noise. A 100 mV peak-to-peak PDN noise would contribute to 100 ps peak-to-peak jitter. In a 2 GHz clocked system, the period is only 500 psec. The jitter from the PDN noise alone would consume the entire timing budget.

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