- 1.1 Signal Integrity Analysis Trends
- 1.2 Challenges of High-Speed Signal Integrity Design
- 1.3 Organization of This Book
1.3 Organization of This Book
Chapter 2, "High-Speed Signaling Basics," is an overview of signaling basics. It describes the fundamental blocks of I/O signaling channels and introduces basic I/O interface design. Without delving into details, it depicts an overall description of I/O interface design, including various clocking and topology options that are often not considered in a traditional signal integrity subject. It also covers major noise components in high-speed I/O links. The basic physics of these noise components are discussed, along with modeling issues.
The remaining chapters are organized into four parts. Part I consists of three chapters on passive-channel modeling. The first chapter, Chapter 3, "Channel Modeling and Design Methodology," presents an overall channel modeling and design methodology. It focuses on a general flow of passive channel modeling. Channel modeling often requires conversion of various network models, and Chapter 4, "Network Parameters," provides conversion formulae for different network parameters. It also presents a few issues in S-parameter modeling, which has recently gained more popularity. This chapter also describes the passivity condition of a network parameter. Finally, Chapter 5, "Transmission Lines," discusses the transmission line model, as well as a popular recursive convolution method and its limitations. Generating transmission line models from measurement data is described in detail. The characteristics of three different interconnect types, a PCB trace, package trace, and on-chip interconnect, are discussed.
Part II considers the simulation and analysis aspects of the channel. Five chapters are devoted to this topic. The first chapter, Chapter 6, "Channel Voltage and Timing Budget," discusses challenges in link performance analysis and reviews conventional voltage and timing budget analysis. The remaining four chapters address these challenges, and cover new simulation methodologies. Chapter 7, "Manufacturing Variation Modeling," introduces Design of Experiment (DoE) in channel analysis. DoE guarantees reliable channel performance for mass-production systems with manufacturing variations. Chapter 8, "Link BER Modeling and Simulation," presents a statistical link simulation framework, which can model both device-timing jitter and voltage noise, in addition to the traditional channel effects. Although the statistical link simulator is a powerful tool, used to predict the link's performance, it has a few serious limitations (such as difficulties in modeling non-linear drivers and accounting for data coding). Chapter 9, "Fast Time-Domain Channel Simulation Techniques," explores a fast-time domain simulator, which can be used in conjunction with the statistical framework to mitigate the issues from a pure statistical approach. A significant portion of jitter or noise can be mitigated by using a proper clocking architecture. Chapter 10, "Clock Models in Link BER Analysis," reviews some of the common clocking architectures and their simulation models for statistical link simulators.
Part III explores the impact of power noise to link performance. Chapter 11, "Overview of Power Integrity Engineering," as its name implies, provides an overview of power integrity engineering. Simultaneous Switching Noise (SSN) analysis is a hot issue for modern high-speed memory interface designs. Chapter 12, "SSN Modeling and Simulation," discusses an efficient and accurate simulation methodology for SSN analysis, using a DDR2 memory system to demonstrate the effectiveness of the presented simulation methodology. Noise mechanisms of SSN for common single-ended signaling technologies are also explained. The reduction of SSN is quite challenging, due to the physical limitation of package designs, and Chapter 13, "SSN Reduction Codes and Signaling," presents bus-coding techniques to mitigate SSN. By using differential signaling or data coding, SSN (due to output power supply noise) is no longer the dominant factor for timing jitter. Power supply noise, on the pre-driver and clock path, induces a significant amount of jitter. Chapter 14, "Supply Noise and Jitter Characterization," discusses the basics of power supply noise–induced jitter (PSIJ). Chapter 14 also covers useful on-chip measurement circuits for measuring power noise and power distribution network (PDN) impedance. The proposed measurement technique is further extended to substrate noise measurement in Chapter 15, "Substrate Noise Induced Jitter."
Part IV is devoted to advanced SI/PI topics. Chapter 16, "On-Chip Link Measurement Techniques," describes on-chip measurement techniques for signal performance and noise measurement. Such features are becoming more important, due to the popularity of 3D packages, such as PoP, SiP, and 3D integration. Modern high-speed links utilize signal-conditioning techniques, used to overcome physical channel limitations, and Chapter 17, "Signal Conditioning," presents a general overview of these equalization techniques. Chapter 18, "Applications," provides three signaling examples to demonstrate the list of common features used in different applications. The first example is an XDR memory system for the high-end PC, game, and graphics applications. Several key architecture-level features, such as FlexPhase for timing adjustment and Dynamic Point-to-Point (DPP) for mitigating multi-drop issues, are also reviewed. The second example is Mobile XDR™ for low-power applications. Additional features, used in Mobile XDR to reduce the interface power, are reviewed in detail. The third example applies these advanced signaling features to the current generation of DDR main memory systems, in order to provide a future roadmap for increasing the data rate. A few highlights of future high-speed interfaces are also presented.