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1.4 Signal and Power Integrity

The I/O signal integrity addresses two major concerns in the electrical design aspects—the timing and the quality of the signal. Timing is critical in a high-speed digital system. Signal timing pertaining to interconnects depends on the delay caused by the electrical length of the interconnect structure where the electromagnetic energy flows from one end to another. It also depends on the modes of the signal propagation—even and odd modes especially in an inhomogeneous medium, that is, microstrip line. The even mode is the behavior of system when driven with identical signals of the same magnitude and same phase. The signal propagation delay can be increased, for the microstrip line, due to the even mode excitation. By contrast, the odd mode is the behavior of a system when it's driven by identical signals of the same magnitude but with different phase. An odd mode type of excitation would make signals faster for the microstrip line. In summary, signal propagation delay in odd mode is shorter than that in the even mode due to signal coupling in a microstrip or embedded microstrip. Lowering even/odd mode coupling results in lower timing jitter. We can achieve less mode coupling by using low k and thinner dielectric PCB in the microstrip systems. However, for a homogeneous medium, such as a stripline, the phase velocity of even and odd mode propagation is the same. Furthermore, we need to carefully examine all other coupling mechanisms due to 3-dimentional structures, for example vias, connectors, and so on. Electromagnetic simulation can help determine acceptable levels of coupling. Chapter 3, "Electromagnetic Effects," describes the fundamentals of electromagnetic theory and its applications for the signal and power integrity analysis.

Signal waveform distortions can be caused by many different mechanisms, but three major noise sources exist. The first noise element is the ISI. For multidrop single-ended interfaces, it is primarily caused by reflection noise due to impedance mismatch, stubs, vias, and other interconnect discontinuities causing energy disruption along the signal path. For high-speed differential interfaces, it is primarily due to the PCB losses, having different transfer function at different frequencies. The effect of ISI causes a reduction in the system voltage margin by reducing the peak and causes an ambiguity in the timing information. The second noise element is the crosstalk noise due to electromagnetic coupling between adjacent signal traces and vias. The third noise element is the power/ground noise due to parasitics of the power/ground distribution system during the drivers' SSO. It is sometimes also called ground bounce, Delta-I Noise, or Simultaneous Switching Noise (SSN). In addition to these three kinds of electrical integrity problems, other Electromagnetic Compatibility (EMC) and Electromagnetic Interference (EMI) problems can contribute to the signal waveform distortions. Signal integrity, power integrity, and EMI are all based on the same electromagnetic fundamentals and cannot be separated.

Power integrity for I/O interfaces is related to the voltage variations in the power/ground network due to the noise. The power/ground noise causes various problems in high-speed systems, such as logic failure, EMI, timing delay, and jitter, as shown in Figure 1.6. The power integrity problems can be identified and root-caused based on the electromagnetic Maxwell's equations. The system noise margin requirements may not be satisfied when power integrity problems happen. The power integrity has several impacts to the I/O signaling as follows:

  1. Signal Quality: Power noise exists on the signals due to the coupling power/ground noise in signal interfaces through signal reference transition.
  2. Timing Delay/Jitter (Lateral SSO push-out or pull-in, slew rate impact): The I/O interface has three stages: logic stage, high-speed I/O stage (clocking and other circuitry such as predrivers), and final stage (driver/receiver circuitry).
    Figure 1.6

    Figure 1.6 Power noise impact on IO signaling

    There is a delay associated with the multiple stages of devices the signal needs to pass through from core logic to the I/O output stage. As the rail voltage fluctuates, the delay through each stage increases or decreases. So the time from an edge leaving the core to the time it arrives at the output of the I/O interface can change with power/ground noise. Also, the signal edge will be faster or slower depending on the power/ground noise. All these internal stages may or may not be tied to the same power/ground networks as the final I/O stage (driver, receiver). Noise coupling from other stages need to be considered when determining the supply noise induced timing variations.
  3. Functionality: Power/ground voltage fluctuations disturb the data in the latch; then logic error, data drop, false switching, or even system failure can occur. This can happen when the noise causes the signal voltage to fall below VIH (input high level) minimum or above VIL (input low level) maximum.
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