1.2 I/O Signaling Standards
Examples of the logic families include Transistor Transistor Logic (TTL), Complementary Metal Oxide Semiconductor Logic (CMOS), Emitter Coupled Logic (ECL), and Bipolar Complementary Metal Oxide Semiconductor Logic (Bi-CMOS). Voltage requirements for the I/O signaling are dependent on the semiconductor process. The I/O standard defines a circuit topology with a logic family. It includes driving current, operating voltage, termination schemes, and switching behaviors .
I/O signaling can be in voltage mode or current mode. In voltage-mode circuits, the information processed by the electric network is represented by nodal voltages. In current-mode circuits, information processed is represented by branch currents. The sensing circuit at the destination determines the logic or signal state. The signal state is determined by the voltage value in voltage mode signaling, whereas it is determined by the current value in current mode signaling.
1.2.1 Single-Ended and Differential Signaling
Single-ended and differential signaling is categorized based on how voltages and currents are observed at the driver and the receiver. Figure 1.2 shows a single-ended signaling link. It comprises a driver, a receiver, and a transmission line from the driver to the receiver.
Figure 1.2 Single-ended link
A single-ended driver has one output port and assumes a common ground or power connection as a reference. For a single-ended receiver, there is one input port that assumes a common ground or power connection as a reference. In this chapter and in Chapter 2, "I/O Interfaces," generic nomenclature is used for power (Power) and ground (Gnd) nodes, for the driver as well as the receiver. Power nodes are electrically different from the driver and the receiver due to PDN parasitics. Similarly, the ground nodes are electrically different for the driver and the receiver.
The single-ended signaling scheme with two input terminals at the receiver is shown in Figure 1.3. Similar to the previous scheme, it also has a single output terminal at the driver. This terminal is referenced to common power or ground.
Figure 1.3 Single-ended link with Vref at RX
However, at the receiver end, there is one input terminal along with a locally generated reference voltage (Vref). This receiver has a differential amplifier, so it is similar to a pseudo differential receiver. Overall link is still a single-ended link. This locally generated Vref is on the Printed Circuit Board (PCB) and is primarily used to compensate the DC and low-frequency voltage drop. A single-ended push-pull driver can be designed in a current mode or a voltage mode configuration .
A single-ended signal has a power or ground reference or both. The referencing scheme can be identified by the proximity of the signal line to the power or ground domains. The proximity of the signal to the power or ground domain tends to make a return path to the domain in high frequencies, because capacitive coupling makes a low impedance path between the signal and that domain. Frequently, unintentional referencing change occurs in complex multilayer PCBs. When the signal is routed on the board from one layer to the other layer, there may be some regions with signal over void. The signal's reference change due to the vertical structure inside of a rather flat power/ground domain structure works as one of the major sources of unintended radial wave propagation. It contributes to signal noise and power delivery noise when it is captured by other structures inside of the PCB. In addition to referencing change, rather loose coupling of single-ended signaling makes it more susceptible to noise than differential signaling. In general single-ended signaling is preferred in many interfaces including Double Data Rate (DDR) memory signaling because of its rather simpler structure, less pincount, and simpler buffer circuit.
Figure 1.4 shows a differential link. A differential driver can be designed in a current mode or a voltage mode configuration . A differential driver has two ports, which are separate from the power or ground connections. At the driver output, the differential signal is referenced from one of its ports to the other ports. At the driver output, two transmission lines are connected to the output ports. These lines are coupled lines: tightly coupled or loosely coupled. Tightly coupled differential links typically perform better at higher data rate and are physically smaller than loosely coupled ones. If the reference power or ground plane is far away, then one line has the other line as a reference. However, for most of the practical systems, due to the vicinity of the reference planes, most of the return current goes through the reference planes. At the input of the receiver, there are two ports, which are different than power or ground connections. At the receiver input, the signal is referenced from one port to the other port. Differential signaling can achieve higher data rates and has low susceptibility to noise. The impact of power/ground noise coupling to signal line on differential signaling is less than that on single-ended signaling. However, differential signaling requires twice the number of wires compared to those for single-ended signaling. More number of wires results in a higher cost of the system. The mismatch of the coupled lines causes common mode fluctuations at the receiver; therefore either a well-designed receiver, well-matched coupled lines, or both are needed to fully utilize the advantages of differential signaling.
Figure 1.4 Differential link
Chapter 2 describes in details single-ended and differential drivers/receivers with the associated currents in different nodes. When the interface is switching, the current is generated on the power and ground nodes of the circuits. This current produces noise at the chip, which gets coupled to the signal lines.