- Chapter 3: Microprocessor Types and Specifications
- Pre-PC Microprocessor History
- Processor Specifications
- SMM (Power Management)
- Superscalar Execution
- MMX Technology
- SSE (Streaming SIMD Extensions)
- 3DNow and Enhanced 3DNow
- Dynamic Execution
- Dual Independent Bus (DIB) Architecture
- Processor Manufacturing
- PGA Chip Packagingx
- Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
- Processor Sockets and Slots
- Zero Insertion Force (ZIF) Sockets
- Processor Slots
- CPU Operating Voltages
- Heat and Cooling Problems
- Math Coprocessors (Floating-Point Units)
- Processor Bugs
- Processor Update Feature
- Processor Codenames
- Intel-Compatible Processors (AMD and Cyrix)
- P1 (086) First-Generation Processors
- P2 (286) Second-Generation Processors
- P3 (386) Third-Generation Processors
- P4 (486) Fourth-Generation Processors
- P5 (586) Fifth-Generation Processors
- Pseudo Fifth-Generation Processors
- Intel P6 (686) Sixth-Generation Processors
- Other Sixth-Generation Processors
- Itanium (P7/Merced) Seventh-Generation Processors
- Processor Upgrades
- Processor Troubleshooting Techniques
First used in the P6 or sixth-generation processors, dynamic execution is an innovative combination of three processing techniques designed to help the processor manipulate data more efficiently. Those techniques are multiple branch prediction, data flow analysis, and speculative execution. Dynamic execution enables the processor to be more efficient by manipulating data in a more logically ordered fashion rather than simply processing a list of instructions, and it is one of the hallmarks of all sixth-generation processors.
The way software is written can dramatically influence a processor's performance. For example, performance will be adversely affected if the processor is frequently required to stop what it is doing and jump or branch to a point elsewhere in the program. Delays also occur when the processor cannot process a new instruction until the current instruction is completed. Dynamic execution allows the processor to not only dynamically predict the order of instructions, but execute them out of order internally, if necessary, for an improvement in speed.
Multiple Branch Prediction
Multiple branch prediction predicts the flow of the program through several branches. Using a special algorithm, the processor can anticipate jumps or branches in the instruction flow. It uses this to predict where the next instructions can be found in memory with an accuracy of 90 percent or greater. This is possible because while the processor is fetching instructions, it is also looking at instructions further ahead in the program.
Data Flow Analysis
Data flow analysis analyzes and schedules instructions to be executed in an optimal sequence, independent of the original program order. The processor looks at decoded software instructions and determines whether they are available for processing or are instead dependent on other instructions to be executed first. The processor then determines the optimal sequence for processing and executes the instructions in the most efficient manner.
Speculative execution increases performance by looking ahead of the program counter and executing instructions that are likely to be needed later. Because the software instructions being processed are based on predicted branches, the results are stored in a pool for later referral. If they are to be executed by the resultant program flow, the already completed instructions are retired and the results are committed to the processor's main registers in the original program execution order. This technique essentially allows the processor to complete instructions in advance and then grab the already completed results when necessary.