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1.6 Overview of This Book

This book systematically presents the latest developments and advancements in jitter, noise, and BER (JNB) and SI. It guides you from the basic math, statistics, circuit, and system models to the final practical applications. It covers fundamental theory, to JNB and SI simulation/modeling, to JNB and SI diagnostics/debug and compliance testing, with an emphasis on two major applications: clock and serial data communications. It tries to keep a good balance and coupling between theory and practical applications.

As you have seen, this chapter is a high-level overview of JNB and SI basics. This chapter introduced the JNB component classification scheme, JNB interrelationship, root-cause mechanisms, JNB measurement references, clock recovery, and associated JNB transfer functions.

Chapter 2 reviews and introduces the basic theories on statistics, linear time-invariant (LTI) systems, and digital signal processing that you need to quantitatively understand and model JNB and its related components. Also introduced in this chapter is the statistical signal process theory that is used to quantify the JNB spectrum and power spectrum density (PSD).

Chapter 3 describes the jitter component in a quantitative manner. Detailed root causes and mathematical models and treatments for each jitter component are given. This chapter lays the necessary physical and mathematical foundation for jitter and noise to warrant the precision of the estimations. Jitter component math models can be applied to noise components similarly.

Chapter 4 discusses jitter, noise, and BER correlatively from the view of statistical signal processing. It first discusses the jitter total PDF and its relationship with the PDFs of its component. It then discusses the noise total PDF and its relationship with the PDFs of its component. It also discusses the joint PDFs, with both jitter and noise being considered. Finally, it discusses the BER cumulative distribution function (CDF) and its relationship to both corresponding jitter and noise PDFs. Applications of two-dimensional eye diagram and BER contour are introduced.

Chapter 5 focuses on jitter separation methods in the statistical distribution domain. Equipped with basic math knowledge, as well as the mechanism and physical nature of each jitter component, you will read about jitter separation. Jitter separation is an important step toward understanding and quantifying jitter components, because in reality the jitter that we observe or measure is a "compound" jitter with many components. Jitter separation methods based on jitter PDF and BER CDF are introduced. The "Tailfit" method in which random jitter PDF is quantified by a Gaussian distribution is first introduced for PDF-based jitter separation. Then the same method is applied to BER CDF-based distribution, in which the random jitter CDF is quantified by the integration of a Gaussian—namely, an error function.

Chapter 6 discusses jitter separation methods in the time and frequency domain. Both spectrum (first moment) and PSD (second moment)-based jitter separation methods are introduced, and associated advantages and disadvantages of each method are given. This chapter also compares statistical PDF/CDF-based methods with spectrum and PSD-based jitter separation methods.

Chapter 7 focuses on clock jitter because it is an important topic for all digital systems, so it deserves a dedicated treatment. New concepts of phase jitter, period jitter, cycle-to-cycle jitter, and their corresponding relationships are discussed. The mathematical relationship between phase jitter, period jitter, and cycle-to-cycle jitter is given in both time and frequency domain. Furthermore, phase jitter and its relationship to the conventional phase noise for quantifying the performance of clock or crystal oscillator in the frequency spectrum domain are also discussed.

Chapter 8 focuses on PLL jitter because it is widely used in clock generation and clock recovery and is an important metric for any high-speed PLL. Jitter at the PLL output and its relationship with PLL building elements such as phase detector (PD), low-pass filter (LPF), voltage control oscillator (VCO), and dividing/multiplying are discussed. Jitter as a function of PLL reference and internal noise sources and transfer functions is derived and applied to PLL and its jitter analysis for second-order, third-order, and general nth-order PLL implementations.

Chapter 9 is dedicated to jitter, noise, and SI mechanisms and root-cause sources or mechanisms for a high-speed link system. Those mechanisms are discussed within the context of link architecture, including its subsystems of transmitter, receiver, channel, and reference clock. For the transmitter, reference clock jitter and voltage driver noise are discussed. For the receiver, jitter from clock recovery circuits and data sampler are the focus. For the channel, various losses in both copper- and optical-based channels are covered. For the reference clock, jitter due to PLL or crystal oscillator, as well as spread-spectrum clocking (SSC), are presented. This chapter also discusses the link jitter budget method using the RJ root-sum-square (RSS) method to ensure the link's interoperability and overall BER performance.

Chapter 10 focuses on quantitative modeling and analysis for jitter, noise, and SI. Modeling and analysis methods are presented for link subsystems of transmitter, receiver, and channel within the framework of the LTI system theory. By using the cascading property of the LTI theorem, signal, jitter, and noise at the channel and receiver outputs are readily obtainable. Important subsystems of equalization and clock recovery are included in the modeling and analysis. For the equalization, both transmitter and receiver equalizations are considered. The modeling and analysis methods introduced in this chapter can give estimations for most advanced serial links today and are scalable to future link advancement given that they are LTI-based.

Chapter 11 is dedicated to the various testing aspects of jitter, noise, and SI. It describes test implications and requirements for the link architectures/topologies operating mechanisms, with a focus on clock recovery and equalization. Testing requirements and methods for links with clock recovery and equalization are presented, covering transmitter, channel or medium, reference clock, and PLL. System test methods such as loopback test also are discussed.

Chapter 12 is an executive summary and overview of the entire book. Future works and trends for JNB and SI at high speed as data rates keep increasing also are discussed.

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