- The Itanium Processor Family: Built on Two Impressive Legacies
- The Progress of Technology at Hewlett-Packard
- At the Start: The Wide Word Project
- Itanium as a New Processor Benchmark
- The Business Drivers Met by Itanium Processor Development
- Envisioning the Utilization of Itanium's Power
- In Summary
At the Start: The Wide Word Project
In 1990, a project that originally was named the "Super Workstation" project, and subsequently rechristened the "PA Wide Word" effort, was inaugurated at the Hewlett-Packard laboratories. The scheduled 1989 meeting date between Frank Carrubba, Director of HP Labs, and John Young, HP CEO, to discuss initiating the project, was probably fitting for a project that was destined to send shocks through the world of processor technology. It so happened that the scheduled meeting time took place exactly when the Loma Prieta earthquake rattled California's fault lines with a sizeable trembler. Director Frank Carrubba recalled that he had just entered John Young's office when the building started to shake and ceiling tiles began to fall. But dismissing the near natural disaster, the meeting was rescheduled and they concluded that the effort should proceed.
The project was established in HP Labs under the leadership of Dick Lampman and Bill Worley. Dick, now Director of HP Labs, served as the administrative director, and Bill acted as the technical director. Bill Worley was one of the most influential members of the design team whose work ultimately culminated in the Itanium Processor Family Architecture. He had led the development of PA-RISC from the early 1980's, and then took a leave of absence outside of HP. It was in 1989 that Frank Carrubba suggested that he be brought back to do what became the wide word project, which led to the meeting with John Young that established the project's charter.
The team's charter was, at its inception, extremely simple. Initially focused upon workstations, the core design requirements remained the same even as the scope of the project grew to encompass the broader range of products available on the market today.
Design an advanced architecture that can move Hewlett-Packard ahead of the competition by establishing a new benchmark for speed, reliability, and ease of transition for legacy systems.
Find ways of making machines provide superior performance by means of an innately superior architecture.
Focus on improving the competitive performance of the workstations that work with the new architecture.
At the same time, ensure that the design also can deliver superior price performance.
The Quadruple Conclusion of the Design Team
With this charter in mind, Bill's design team analyzed existing architectures and came to four conclusions that would prove instrumental in developing the Intel Itanium architecture. This work built upon ideas that had taken shape earlier in their work on PA-RISC, lessons learned with earlier vector and VLIW systems, and work already underway in HP Labs under Bob Rau:
First, that the generation beyond RISC would have to be designed explicitly to execute multiple operations in every machine cycle. Already, it was clear that there would be significant hardware complexity trying to reach this goal for RISC architectures. With the PA-RISC 8000, for example, there were over 850,000 transistors devoted just to reordering the instructions and making some of them run in parallel. The entire previous generation PA-RISC processor chip had used only 850,000 transistors for the entire processor.
That there was inherent mathematical complexity in out-of-order superscalar RISC machines that would prevent them ever from sustaining over about four instruction executions per cycle in the best-case scenario. Since then, observations and testing of out-of-order superscalar type designs have validated this conclusion.
That for any architecture, including out-of-order superscalar RISC, the compiler explicitly must schedule instructions, in order to sustain execution of multiple instructions per cycle. This conclusion strongly implies that hardware should be kept simple, and that it should be straightforward for a compiler to schedule the concurrent execution of instructions.
Finally, a clean drawing board was needed in order to make the architecture scalable well beyond existing limits, while also enabling significantly simpler hardware.
With Bill Worley as the technical director, the program began to function within HP Labs. With an eye to pulling together experts in all the important critical areas, the team began to work on improving every aspect of the project's design. Silicon design, circuit design, logic design, simulation, packaging, cooling, compiler, operating system, and architecture experts all were tapped to create the new processor architecture.
Seeds of a New Partnership
By the end of 1993, Hewlett-Packard approached Intel about continuing this research as part of a partnership. It was a fortuitous time for HP to approach Intel. Given the close community of high-level designers, there was a fair amount of buzz in the air and correspondingly a lot of curiosity about what exactly was going on in HP Labs to occupy such highly qualified designers.
Additionally, the costs for building state-of-the-art silicon fabrication plants had continued to skyrocket, reaching the level of billions of dollars per plant. Rather than massive investments in HP facilities to produce the new chip, or major dependencies upon independent fabrication plants, Bill Worley had a different idea:
"In July of 1992 I proposed to the executive committee in HP Labs's annual review that what HP should do is develop our architectural ideas into a product that would become a defacto industry standard, and for that we had to partner, ideally, with a semiconductor manufacturer. At the time, we didn't know who that might be, but Intel was a premier candidate."
Certainly, this was a successful process for Intel, as it was the driving force behind building the x586 processor, known more commonly as the first generation of the Pentium. Once this field began to be mined out, it was time to focus on new ideas at the high end of the marketplace, where HP had a tremendous history of high-performance processor development expertise.
Intel's COO Paul Otellini once noted that some people in the industry "have described microprocessor architecture as the plagiarists of all time because of what they did for the first 25 years of their historywhere they took every idea that they ever perceived in computer science and put it on a chip."
Complimentary Expertise and Market Forces at HP and Intel
Timing, as they say, is everything. As it turned out, the timing was right for the Itanium architecture, as the notion of collaborating on a processor that was beyond the Pentium and RISC became a unifying force for both companies. In the past, Intel's architecture design had been made with a specific goal in mind. This goal was to enable more and more capabilities for users at lower and lower costs. This was an extremely effective way to bring the benefits of standardized computing into desktops, workstations, midrange and even low-end servers.
Similarly, Hewlett-Packard was casting about for the best method to capitalize on our advanced silicon designs. The opportunity to bring the same economies of scale benefits to mainframe class replacements that had been brought to minicomputers in the prior generations was a major one. As Paul Otellini succinctly put it, Intel wanted to move 'up market', and Hewlett-Packard wanted to be able to reduce costs and take advantage of design improvements simultaneously
Intel turned out to be the ideal partner for HP in terms of interest in the product, processor architecture and design expertise, and had the ability to bring the volume design and manufacturing capabilities to bear. Given their long-term involvement in processor design, both Intel and HP got a platform with a tremendous technological pedigree. This legacy was a very attractive one for both computer buyers and application developers.
In essence, the Itanium architecture allowed HP and Intel to design a processor architecture that met the cost function, shattered the speed barrier, and remained true to the design standard of simplicity. It was this standard that led to the development of the Explicitly parallel Instruction Computing (EPIC) architecture, which we discuss in more detail in Chapter 7. The goal of EPIC architecture, as Bill Worley put it, was to do away with all unnecessary complexity in the hardware to enable all of the transistors on the chip to contribute to performance.