- Itanium Mission Statement
- The Itanium Processor Family
- Itanium RAS Features
- Reasons for Itanium®-based Platform Value
- Highly Parallel Architecture
- Investment Protection
- Choice and Breadth of Operating Systems and Applications
- Enterprise Technology
- How Itanium Architecture Affects Enterprise Computing
- In Summary
Highly Parallel Architecture
The highly parallel architecture of the Itanium architecture allows the processor to get more things done during each 'clock cycle'. There are typically two ways to speed up the performance of a processor. The one that the general public understands and follows is to increase the 'clock speed' of a processor. For years, this has been the initial benchmark as to how to measure the speed of a chipa 500Mhz Pentium versus a 200Mhz Cyrix chip, for example.
Members of the Itanium processor family will have a clock speed of one gigahertz and greater. Of course, we're all excited about being able to hasten the clock speed to such a degree. Increasing the clock rate will improve performance, but the processor is still bound by the architecture that defines its operation. For example, the processor may be an early implementation of RISC, which will attempt to get only a single instruction completed per cycle.
Imagine the performance gain from completing two instructions per clock cycle instead of one. By doing two things in parallel, it's the equivalent of doubling the clock speed on the microprocessor. Consider that if you had a 500Mhz chip that could process two instructions per clock cycle, you would end up with a one-gigahertz microprocessor without the costs associated with the higher clock rate.
This ability to make these leaps of performance was the reason we made the step in RISC to move to what's called 'superscalar out-of-order execution RISC'. The end goal was specifically to be able to do more things in parallel, and create a speed gain where previously, the main method was to keep increasing clock speed and changing the manufacturing process to "shrink" the chip
HP and Intel created EPICan explicitly parallel instruction computing architecture, which is the heart of why the Itanium processor family can create its unique price-performance signature. This allows us to go from a slightly more than one instruction per cycle to up to 6 instructions per cycle with the current generation of processors. This level of parallelism is probably not likely over an entire application, but by getting a boost in even a couple of critical loops, the overall effect on the speed of processing can be significant.
In performance tests in the lab, we've seen 1 gigahertz Itanium processors running alongside 2.6-gigahertz chips, and the Itanium processors are getting more usable application work donebecause of the unique architecture.
The magic of EPIC is in its parallelism. Of course, it does take some work in the compiler, and it does take some sorting out to queue up the information to the microprocessor; you have to know that you can do certain things in parallel. And the future of this technology is just beginning. As compilers get better, and we continue our research into the methods of properly utilizing parallel architecture, we'll be able to get even more speed and performance gains out of this processor family.