Home > Articles > Certification > CompTIA

  • Print
  • + Share This
This chapter is from the book

Memory Pages

Typically, memory is divided into chunks (or blocks). At the main memory level, a chunk is referred to as a memory page. At the cache level, a chunk is called a cache block or a cache line. Keep in mind that if a register is 8 bits wide, a cell contains one of the bits in that register. Technically, only a CPU has registers. Memory chips have capacitors and transistors.

The memory controller keeps track of the state and location of the charges held in the capacitors and transistors of a memory chip, as we indicated earlier, in our printing business story. This combination of states and locations is called an address. The charges in the memory chips are created by the original byte transmissions, coming from the CPU's registers. The CPU sends data to memory in order to empty its registers for more calculations.

In other words, the CPU has some information it wants to get rid of. It sends that information to the memory controller. The memory controller shoves it into whichever capacitors are available and keeps track of where it put the data. It keeps track of the bits by assigning memory addresses to each bit of information.

Ranges

Changes in memory chips and controllers are similar to how flat, one-page spreadsheets developed the concept of named ranges. DRAM is usually accessed through paging. A page is a related group of bytes (with their bits), similar to a range on a spreadsheet. It can be from 512 bits to several kilobytes, depending on the way the operating system is set up.

Without ranges, a spreadsheet formula must include every necessary cell in the spreadsheet. For example, we might have a formula something like =SUM(A1+B1+C1+D1+E1). Now suppose that we assign cells C1, D1, and E1 to a range, and call that range "LastWeek." We can now change the formula to include the range name: =SUM(A1+B1+"LastWeek").

When a spreadsheet formula uses a named range, this is analogous to the memory controller giving a unique name to a range of charges. This range of charges is called a page address, and with a page address, the controller doesn't have to go looking for data in every single capacitor or transistor.

Fast Page Mode (FPM)

Dynamic RAM (DRAM) originally began with Fast Page Mode (FPM) back in the late 1980s. In fast page mode, the memory controller makes an assumption that the data read/write following a CPU request will be in the next three pages (ranges), very much like a cache. This is somewhat like having a line of letters all ready to go in the toy stamp we spoke about in our printing business story.

Using FPM, the controller doesn't have to waste time looking for a range address for at least three more times: it can read-assume-assume-assume. Note the three pauses, as we'll mention burst cycles in a moment.

NOTE

When the controller passes through the memory chip, it turns off something called a data output buffer when it reads the page it just read or wrote to. This process takes approximately 10 nanoseconds.

Fast Page Mode is capable of processing commands at up to 50 ns. Fifty nanoseconds is fifty billionths of a second, which used to be considered very fast. Remember that the controller first moves to a row; then to a column; then retrieves the information at an X-Y coordinate—a matrix address.

Once the information is validated, the controller hands it back to the CPU. The column is then deactivated, and the data output buffer is turned off. Finally, the column is prepared for the next transmission from the CPU. The memory enters a 10 ns wait state while the capacitors and transistors are precharged for the next cycle.

Extended Data Output (EDO) RAM

FPM evolved into Extended Data Out (EDO) memory. The big improvement in EDO was that once the column of data was deactivated, the data remained valid until the next cycle began. In other words, FPM removed the data bits in the column address and deactivated the column (data output buffer). EDO, on the other hand, kept the data output buffer active until the beginning of the next cycle, leaving the data bits alone.

EDO memory is sometimes referred to as hyper-page mode, and is a specially manufactured chip that allows a timing overlap between successive read/writes. The data output buffers are not turned off when the memory controller finishes reading a page. Instead, the CPU determines the start of the deactivation process when it sends a new request to the memory controller. The result of this overlap in the process is that EDO eliminated the 10 ns. per cycle delay of fast page mode, generating faster throughput.

Both FPM and EDO memory are asynchronous. (In the English language, the "a" in front of synchronous is called a prefix. The "a" prefix generally mean "not," or "the opposite.") In asynchronous memory, the memory controller and the system clock are not synchronized. DRAM is asynchronous memory. In asynchronous mode, the CPU and memory controller have to wait for each other to be ready before they can transfer data. Remember that everything on an asynchronous motherboard listens to the clock ticks coming from the motherboard oscillator.

Originally, motherboard clocks ran between 5–66MHz. The early x86 processors ran at 5–200MHz. When Pentium Pro motherboards stabilized at 66MHz, CPU speeds went up to between 200MHz and 660MHz. Suppose a motherboard has a 66MHz clock with a clock multiplier of 2. In this situation, the CPU runs at 133MHz (66 * 2). Remember, the CPU runs at the speed of the motherboard clock.

Now suppose a memory chip is synchronized to that same motherboard's 66MHz clock. The memory controller will have to wait 2 clock ticks before it can interrupt the CPU, unless it accidentally happens to catch the CPU at exactly the right time. Think about it: the CPU is hearing two ticks for every one tick the memory controller is hearing. If the CPU processes one instruction for every clock tick, then it will do two things before it's ready to be interrupted by the memory controller. This makes the controller seem a bit slow in the head.

Supplementary Information

If you choose, you may jump to the "Types of RAM" section at this time. This section is a more technical discussion of wait states and the memory standards used in rating memory performance.

A 60 ns. DRAM module, using fast page mode, might run in 5-3-3-3 burst mode timing. The first access takes 5 cycles (on a 66MHz system), or about 75 ns. The next three accesses take only 3 cycles, because they "assume" the range addresses. It happens that this works out to about 45 ns, with a ninety nanosecond savings in time (about 40 percent). Regular old page mode would be 5-5-5-5 burst mode.

EDO RAM became popular for a time, with a typical burst cycle of 5-2-2-2, yielding about a 22 percent savings in time over FPM memory. 50-nanosecond FPM isn't used anymore. Both FPM and EDO memory eventually gave way to Synchronous DRAM (SDRAM), then to Rambus memory, then to DDR-SDRAM (discussed later in this chapter). SDRAM developed a burst cycle of 5-1-1-1, which is even faster than EDO RAM, so SDRAM became the most popular type of memory toward the end of the 1990s.

The PC100 Standard

The speed of the actual memory chips in a module is only part of how we evaluate memory speed. The other factor is the underlying printed circuit board. Due to the physics of electricity and electronic parts, a module designed with parts that can run at 100MHz may never reach that speed. It takes time for the signals to move through the wire, and the wire itself can slow the signal speed. This led to the same old ratings problems that processors were causing.

Motherboard speeds eventually increased to 100MHz, and CPU speeds went beyond 500MHz. The industry decided that the original SDRAM chips should be synchronized at 100MHz. Someone had to set the standards for the way memory modules were clocked, so Intel developed the PC100 standard. This initial version of the standard made sure that a 100MHz module was really capable of, and really did run at 100MHz. Naturally, this created headaches for memory manufacturing companies, but the standard really helped in determining system performance.

The PC100 SDRAM modules required 8 ns DRAM chips, capable of operating at 125MHz. This provided a margin of error, making sure that the overall module would be able to run at 100MHz, according to the standard. The standard also called for a correctly programmed EEPROM, on a properly designed circuit board.

At 100MHz and higher, timing is absolutely critical, and everything from the length of the signal traces to the construction of the memory chips themselves is a factor. The shorter the distance the signal needs to travel, the faster it runs. Noncompliant modules, those that didn't meet the PC100 specification, could significantly reduce the performance and reliability of the system. The standard caught on. Note that unscrupulous vendors would sometimes use 100MHz SDRAM chips and label the modules as PC100 compliant, a similar situation occurred with processor chips (mentioned in the next chapter). This didn't necessarily do any harm, but consumers weren't getting what they were told they were getting.

As memory speeds increased, the PC100 standard was upgraded to keep pace with the new modules. Intel released a PC133 specification, synchronized to 133MHz, and so it went. PC800 RDRAM was released to coincide with the 800 series chipset, running at 800MHz, and these days, we see a PC1066 specification, designed for high-speed RDRAM memory. As bus speeds and module designs change, so too does the specification.

  • + Share This
  • 🔖 Save To Your Account

InformIT Promotional Mailings & Special Offers

I would like to receive exclusive offers and hear about products from InformIT and its family of brands. I can unsubscribe at any time.

Overview


Pearson Education, Inc., 221 River Street, Hoboken, New Jersey 07030, (Pearson) presents this site to provide information about products and services that can be purchased through this site.

This privacy notice provides an overview of our commitment to privacy and describes how we collect, protect, use and share personal information collected through this site. Please note that other Pearson websites and online products and services have their own separate privacy policies.

Collection and Use of Information


To conduct business and deliver products and services, Pearson collects and uses personal information in several ways in connection with this site, including:

Questions and Inquiries

For inquiries and questions, we collect the inquiry or question, together with name, contact details (email address, phone number and mailing address) and any other additional information voluntarily submitted to us through a Contact Us form or an email. We use this information to address the inquiry and respond to the question.

Online Store

For orders and purchases placed through our online store on this site, we collect order details, name, institution name and address (if applicable), email address, phone number, shipping and billing addresses, credit/debit card information, shipping options and any instructions. We use this information to complete transactions, fulfill orders, communicate with individuals placing orders or visiting the online store, and for related purposes.

Surveys

Pearson may offer opportunities to provide feedback or participate in surveys, including surveys evaluating Pearson products, services or sites. Participation is voluntary. Pearson collects information requested in the survey questions and uses the information to evaluate, support, maintain and improve products, services or sites, develop new products and services, conduct educational research and for other purposes specified in the survey.

Contests and Drawings

Occasionally, we may sponsor a contest or drawing. Participation is optional. Pearson collects name, contact information and other information specified on the entry form for the contest or drawing to conduct the contest or drawing. Pearson may collect additional personal information from the winners of a contest or drawing in order to award the prize and for tax reporting purposes, as required by law.

Newsletters

If you have elected to receive email newsletters or promotional mailings and special offers but want to unsubscribe, simply email information@informit.com.

Service Announcements

On rare occasions it is necessary to send out a strictly service related announcement. For instance, if our service is temporarily suspended for maintenance we might send users an email. Generally, users may not opt-out of these communications, though they can deactivate their account information. However, these communications are not promotional in nature.

Customer Service

We communicate with users on a regular basis to provide requested services and in regard to issues relating to their account we reply via email or phone in accordance with the users' wishes when a user submits their information through our Contact Us form.

Other Collection and Use of Information


Application and System Logs

Pearson automatically collects log data to help ensure the delivery, availability and security of this site. Log data may include technical information about how a user or visitor connected to this site, such as browser type, type of computer/device, operating system, internet service provider and IP address. We use this information for support purposes and to monitor the health of the site, identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents and appropriately scale computing resources.

Web Analytics

Pearson may use third party web trend analytical services, including Google Analytics, to collect visitor information, such as IP addresses, browser types, referring pages, pages visited and time spent on a particular site. While these analytical services collect and report information on an anonymous basis, they may use cookies to gather web trend information. The information gathered may enable Pearson (but not the third party web trend services) to link information with application and system log data. Pearson uses this information for system administration and to identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents, appropriately scale computing resources and otherwise support and deliver this site and its services.

Cookies and Related Technologies

This site uses cookies and similar technologies to personalize content, measure traffic patterns, control security, track use and access of information on this site, and provide interest-based messages and advertising. Users can manage and block the use of cookies through their browser. Disabling or blocking certain cookies may limit the functionality of this site.

Do Not Track

This site currently does not respond to Do Not Track signals.

Security


Pearson uses appropriate physical, administrative and technical security measures to protect personal information from unauthorized access, use and disclosure.

Children


This site is not directed to children under the age of 13.

Marketing


Pearson may send or direct marketing communications to users, provided that

  • Pearson will not use personal information collected or processed as a K-12 school service provider for the purpose of directed or targeted advertising.
  • Such marketing is consistent with applicable law and Pearson's legal obligations.
  • Pearson will not knowingly direct or send marketing communications to an individual who has expressed a preference not to receive marketing.
  • Where required by applicable law, express or implied consent to marketing exists and has not been withdrawn.

Pearson may provide personal information to a third party service provider on a restricted basis to provide marketing solely on behalf of Pearson or an affiliate or customer for whom Pearson is a service provider. Marketing preferences may be changed at any time.

Correcting/Updating Personal Information


If a user's personally identifiable information changes (such as your postal address or email address), we provide a way to correct or update that user's personal data provided to us. This can be done on the Account page. If a user no longer desires our service and desires to delete his or her account, please contact us at customer-service@informit.com and we will process the deletion of a user's account.

Choice/Opt-out


Users can always make an informed choice as to whether they should proceed with certain services offered by InformIT. If you choose to remove yourself from our mailing list(s) simply visit the following page and uncheck any communication you no longer want to receive: www.informit.com/u.aspx.

Sale of Personal Information


Pearson does not rent or sell personal information in exchange for any payment of money.

While Pearson does not sell personal information, as defined in Nevada law, Nevada residents may email a request for no sale of their personal information to NevadaDesignatedRequest@pearson.com.

Supplemental Privacy Statement for California Residents


California residents should read our Supplemental privacy statement for California residents in conjunction with this Privacy Notice. The Supplemental privacy statement for California residents explains Pearson's commitment to comply with California law and applies to personal information of California residents collected in connection with this site and the Services.

Sharing and Disclosure


Pearson may disclose personal information, as follows:

  • As required by law.
  • With the consent of the individual (or their parent, if the individual is a minor)
  • In response to a subpoena, court order or legal process, to the extent permitted or required by law
  • To protect the security and safety of individuals, data, assets and systems, consistent with applicable law
  • In connection the sale, joint venture or other transfer of some or all of its company or assets, subject to the provisions of this Privacy Notice
  • To investigate or address actual or suspected fraud or other illegal activities
  • To exercise its legal rights, including enforcement of the Terms of Use for this site or another contract
  • To affiliated Pearson companies and other companies and organizations who perform work for Pearson and are obligated to protect the privacy of personal information consistent with this Privacy Notice
  • To a school, organization, company or government agency, where Pearson collects or processes the personal information in a school setting or on behalf of such organization, company or government agency.

Links


This web site contains links to other sites. Please be aware that we are not responsible for the privacy practices of such other sites. We encourage our users to be aware when they leave our site and to read the privacy statements of each and every web site that collects Personal Information. This privacy statement applies solely to information collected by this web site.

Requests and Contact


Please contact us about this Privacy Notice or if you have any requests or questions relating to the privacy of your personal information.

Changes to this Privacy Notice


We may revise this Privacy Notice through an updated posting. We will identify the effective date of the revision in the posting. Often, updates are made to provide greater clarity or to comply with changes in regulatory requirements. If the updates involve material changes to the collection, protection, use or disclosure of Personal Information, Pearson will provide notice of the change through a conspicuous notice on this site or other appropriate way. Continued use of the site after the effective date of a posted revision evidences acceptance. Please contact us if you have questions or concerns about the Privacy Notice or any objection to any revisions.

Last Update: November 17, 2020