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Memory Buses

We measure memory speed in nanoseconds (billionths of a second). On the other hand, we measure CPU speed in megahertz (millions of cycles per second) or gigahertz (billions of cycles per second). Blending the two, we come up with how many million instructions per second (MIPS) a processor can complete. Disk speed is measured in milliseconds (thousandths of a second), and a hard disk typically reads information at around 100 reads per second—not to be confused with Revolutions Per Minute (RPM). A floppy disk generally performs 10 reads per second, while RAM can make a billion reads per second. So moving data in and out of RAM is extremely fast—much faster than moving it to and from a disk.

Modern chipsets use a North-South bridge architecture, as we discussed in Chapter 2. The CPU no longer directly connects with the system memory, but works in combination with the North bridge and the memory controller to move data bits in and out of main memory. In Figure 3.1 we can see how the CPU uses additional buses to connect with the L-1 cache inside the processor housing and the L-2 cache outside the housing. In modern computers, the L-2 cache is usually internal to the housing, and we might find an external Level 3 (L-3) cache. The A+ exam covers only Level 1 and Level 2 caches, and the L-2 cache is considered to be outside the CPU.

A CPU has a number of very small places inside the housing where it stores bits and bytes of data. We've also seen that memory modules store bits of data in capacitors or transistors. Technically speaking, the storage places inside a CPU are called registers. The data storage places on a DIMM are called cells. Data is constantly moving in and out of registers and being temporarily stored in main memory or cache memory. Figure 3.1 is a highly stylized drawing of the internal registers, the internal L-1 cache, the external L-2 cache, and the two memory buses. Remember that the PCI bus, or expansion bus, is connected to the other end of the North-South bridge—the South bridge. Refer to Figure 2.10 in Chapter 2.

Figure 3.1 Different memory pathways.

Front Side Bus

The North bridge handles fast data transfers into and out of system memory and the AGP, working with the memory controller over a bus. This bus is the subject of a fair amount of controversy, with some people calling it the system bus and others calling it the Front Side Bus (FSB). You also may find references to a processor bus or a memory bus. For the moment, we'll refer to it as the front side bus. System performance is based on a timing relationship between the CPU and the FSB, with the bus being clocked at a reduced multiple of the processor. In other words, if you have an 800MHz Pentium 4, with an FSB clocked at 133MHz, the FSB is running at one sixth the speed of the chip. Doubling the speed of FSB throughput, making it 266MHz, increases the bus speed to one third of the chip speed. Much of today's performance ratings are based on increasing the clock speed of the front side bus.

Here's another example of FSB speed in relation to CPU speed. Suppose that you have an 800MHz Celeron processor in a machine with a front side bus clocked at 3:1, or a third of the processor speed. Data transfers take place at 266MHz. Now suppose you have a machine with a 1GHz Pentium 4 and an FSB clocked at 4:1, or a quarter of the processor speed. In this instance, data transfers take place at 250MHz (1,000 / 4). Which is the better system, the 800MHz or 1GHz machine? Can we say that a Pentium 4 is always better than a Celeron?

You begin to see that performance is very much tied to the speed of the front side bus. This isn't to say that the entire system is hanging on the FSB, but to point out that performance is becoming a combined measure of many different components.

Backside Bus

The backside bus, shown in Figure 3.1, connects the CPU with an external L-2 cache. Because the data path is extremely short and Level 2 caches are usually comprised of SRAM, data transfers take place at about the same speed as the CPU. We discuss the L-1 and L-2 caches, as well as how a cache operates, in the next sections, but you should have a picture of how the various components of memory are connected. We discuss SRAM in the "Types of RAM" section.

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