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1.7 Reliability Simulation Tools

Nowadays, semiconductor companies have a considerable interest in reliability simulation tools. These simulation tools predict the degradation in circuit performance after a specified period of operation, for a targeted reliability hazard. These tools are listed in Table 1.5.

Table 1.5. Reliability simulators and their targeted reliability hazards; courtesy [301]. Reprinted from Microelectronics Reliability, vol. 40, 2000, S. Minehane, R. Duane, P. O'Sullivan, K.G. McCarthy, and A. Mathewson, "Invited Paper: Design for Reliability," pp. 1285-1294, „ 2000, with permission from Elsevier Science Ltd.

Table 1.2

To provide a general overview of state-of-the-art reliability simulation, we shall study the characteristics of the BERT suite of tools (BERT is an acronym for Berke-ley reliability tools). BERT provides several tools for simulating various hazards such as hot-carrier injection, electromigration and oxide reliability.

The hot-carrier simulation tool provided by BERT is called CAS (circuit aging simulator) [238]. CAS can be used to predict the hot-carrier degradation of individual devices, in the form of a lifetime figure, as well as the circuit performance, using the degraded parameter set for each device, after a specified period of time.

The NMOS lifetime model used by CAS is the Berkeley hot-carrier lifetime model [182]:

In the above model, m and C denote technology-dependent parameters, W denotes the channel width, and Ids and Isub represent the drain-to-source and substrate currents, respectively. CAS requires the following inputs: (1) model parameters for the device extracted at increasing levels of hot-carrier degradation; (2) circuit description, and (3) a set of degradation constants, derived from the results of accelerated hot-carrier tests performed on numerous devices. CAS uses a circuit simulator to calculate node currents and voltages, based on which it computes drain and substrate currents for each device. The post-processing phase of CAS computes a coefficient called age for each transistor, as follows:

In the above model, the parameter H is linearly related to C (from the previous equation). Each stressed transistor has an age parameter (together with its other device parameters), and this parameter is used to compute a set of 'degraded' parameters. The circuit is then re-simulated using the degraded parameter set in order to predict its performance as a function of time.

BERT can simulate electromigration effects in two different ways. In the first approach, the user simply provides a circuit schematic and a desired reliability specification (failure rate after a certain number of hours of operation), before the layout phase. The simulator calculates the node current and voltage waveforms based on pre-layout information and passes these waveforms to the electromigra-tion analysis program. This program provides guidelines for choosing the width and length of each interconnect during layout, and also provides a safety factor for each contact or via in the circuit. In the second mode of operation, the circuit elements such as interconnects, contacts and vias are extracted from the layout geometry by a special program which generates the node waveforms for the circuit. Analysis of electromigration is then performed and the results are back-annotated onto the layout as current density contour maps. The tool marks the critical interconnects, contacts, and vias from an electromigration standpoint, provides information on the failure rate and the cumulative failure percentage, and produces an advisory for layout modification.

The oxide reliability simulation engine in BERT is the circuit oxide reliability simulator (CORS) [376]. This simulator requires as input: (1) the test data, consisting of a distribution of time to breakdown, measured on a population of capacitors that are subjected to a constant voltage stress; (2) a circuit description, listing the number of devices and the area and edge components of every device; and (3) the input stimuli to be applied by the simulator. Note that the lifetime calculations assume that these stimuli are applied repeatedly over the entire lifetime of the device. The simulator computes the bias on each device using SPICE-like circuit simulation. Then it combines the bias, area and edge information with the test data, using area and field acceleration models, and calculates failure probability of each device and of the overall circuit. From these failure probability values, the user can determine if the circuit will meet a reliability specification at a given time of operation, say, after five years.

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