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1.2 Impact of Scaling on Reliability

According to the Semiconductor Industry Association's (SIA's) 1998-updated International Technology Roadmap for Semiconductors (ITRS) [452], and its predecessor, the National Technology Roadmap for Semiconductors (NTRS) [453], the minimum feature size of mainstream CMOS devices will be scaled down to about 0.07 mm for (future) 64-Gb DRAMs. Moreover, according to the NTRS roadmap, DRAM processing will continue to be the technology driver up to a memory cell density of 64 Gb per chip (achieved around 2008), and the existing pace of new DRAM technologies in intervals of three years will be sustained. The technology characteristics are shown in Table 1.1.

However, new generations of memory devices will be accompanied by reliability problems due to scaling down of feature sizes. Some of these issues are described in the following sections. See Figure 1.1 for a classification of these problems.

Figure 1.1Figure 1.1. Classification of reliability problems caused by technology scaling

1.2.1 Supply voltage and power constraints

The basic principle behind scaling is to maintain the electric field in the device constant while shrinking its dimensions. This can be achieved by scaling down the geometrical feature size and the supply voltage by the same factor. However, scaling down the supply voltage is associated with standardization and delay problems in the chip. Therefore, the supply voltage has traditionally been reduced by a smaller factor than the gate oxide thickness, producing larger gate oxide field strengths from the 1- to 64-Mb DRAM generations. Power constraints on the chip may require the reduction of supply voltage for RAMs in the gigabit range. On the other hand, in case of DRAMs, the supply voltage may need to be kept high to maximize the data retention time and to provide sufficient stored charge. Table 1.1 predicts the change in oxide thickness of DRAMs together with reduction in supply voltage. To pass the full VDD voltage to the storage capacitor of a DRAM cell, the gate voltage of the access NMOS transistor must be kept at about 1.2 V above VDD to compensate for its threshold voltage drop and its reverse-bias effect. Hence, the word-line voltage will be from 1.5 times VDD for the 256-Mb DRAM generation to 2.3 times VDD for the 64-Gb generation. Therefore, to prevent a sharp increase in the electric field strength across the gate oxide of DRAM access transistors, different scaling approaches are required for the gate oxides of DRAM access transistors compared to transistors used for logic applications.

As observed by Krautschneider et al. [227], there was a clear tendency toward higher field strengths from 1- to 64-Mb DRAM generations. As we continue into the regime of gigabit DRAM technology, this tendency seems unlikely because the increase in the DRAM gate oxide area may be accompanied by an increase in the total number of layout defects per DRAM chip [453]. This problem is compounded by higher field crowding and local oxide thinning at corners, because of an increase in the perimeter of the gate oxide area. Therefore, it is expected that the maximum electric field will be kept approximately constant or even slightly decreased, from the 256-Mb to 64-Gb DRAM generations, as can be calculated from Table 1.1.

For microprocessors and logic chips, the power consumption is proportional to , where Cox denotes the oxide capacitance per unit area and f denotes the operating frequency. An increase in f and Cox must be compensated by a decrease in the supply voltage to restrict the power consumption. Krautschneider et al. [227] illustrate a scaling scenario for microprocessors and logic chips that aims to restrict the power consumption. It is found that the total power consumption per chip will still increase because of the growing chip area, warranting an appropriate packaging and board design technology. Therefore, power constraints will drive down supply voltages and tend to limit the maximum electric field during operation of processor chips corresponding to gigabit DRAM generations.

1.2.2 Threshold voltage control

Controlling the threshold voltage is a major problem with scaled-down MOS transistors. Typically, ion implantation is used to adjust the threshold voltage. Fluctuations in threshold voltage can be caused by statistical variation in the distribution of implanted dopant atoms in the depletion region. A very few transistors in the chip may be thrown out of the specified threshold voltage limits for correct operation because of such fluctuations [84, 298]. In addition to these statistical fluctuations caused by the varying number of dopant atoms in the channel, sometimes there is an average shift in the threshold voltage to a lower value due to the discrete nature of dopant atoms in the channel, as discovered by Wong and Taur [498]. This shift is between -15 to -34 mV for channel lengths of 0.1 mm. This discrete nature of dopant atoms causes an inhomogeneous channel potential that allows early turn-on in parts of the channel, causing both a shift in the threshold voltage and degradation of the subthreshold slope.

1.2.3 Gate oxide reliability

Gate oxide reliability is affected adversely by:

  • Physical defects during manufacture, such as local oxide thinning which can give rise to high electric field strengths

  • Penetration of boron, a dielectric component and dopant that causes undesirable threshold voltage shifts and a greater trapped charge density and lower stability of the gate oxide

  • High electric field strengths across the gate oxide

  • Oxide thicknesses below approximately 4 nm, which lead to direct tunneling, producing an oxide current, called stress-induced leakage current (SILC) [375], over and above the current that is caused by the Fowler-Nordheim tunneling mechanism

  • Electron and, especially, hole trapping in the oxide, which may cause dielectric breakdown

  • Electrochemical factors caused by mobile ions, such as Na+ and H+, that may enhance the electric field and cause breakdown [213]

  • Temperature acceleration of the electric field [213]

  • Interface softening due to total defect generation produced jointly by impact ionization and trap creation, which in turn, is influenced by the trap generation rate [10] and the formation of a locally generated trap path within the oxide [102].

The oxide breakdown process is a function of time, and is thereby also known as time-dependent dielectric breakdown (TDDB). Krautschneider et al. [227] plotted the time to breakdown for defect-free gate oxide versus the reciprocal of the electric field strength and obtained a straight line with data obtained from [181]. They found that a maximum field of 7.5 MV/cm can be sustained for 10 years by the gate oxide.

Wafer-level screening can be cost-effectively employed to check the defect density of gate oxides. Such screening can be done using high-voltage stress tests for a short period of time prior to the source-drain implantation. This is feasible since the maximum applicable voltage prior to source-drain implantation is not limited by the P/N junction breakdown. To increase oxide lifetime and suppress boron penetration, nitridation of the oxide [4,125] is a promising technique. Other techniques for higher oxide stability include the addition of chlorine (about 2 to 3% HCl to the oxidants) to increase the breakdown voltage, hydrogen annealing to increase the breakdown field [266], use of tunneling gate oxides [305] to improve the transcon-ductance with minimum oxide thicknesses of 4 nm, and reduction of mechanical stress and oxidation at temperatures below 850°C to reduce the trap density of holes [440] and to counteract the boron penetration [468]. The latent damage to the Si/SiO2 interface caused by high voltage stress tests can also be removed by annealing at 900°C [214]. Boron penetration can also be reduced by tilting the wafer at about 60° during source-drain implantation [516]. The columnar microstructures and pinholes of the polycrystalline silicon are believed to favor boron penetration [516]; hence, a tilted ion implantation counteracts this mechanism.

1.2.4 Hot carrier degradation

For very deep submicron technologies approaching the 0.1-mm regime, when gate oxide thicknesses and channel lengths are scaled down without proportionately scaling down the power supply voltage, a very high electric field (on the order of 107 V/cm) is produced near the drain. Injection of hot carriers into the gate oxide (SiO2) layer from the passivation overlayer produces charges in the oxide by trapping carriers (electrons and holes). This results in damage to the interface between the gate insulator and silicon and would eventually leads to failure due to degradation in the device current to abnormally high levels and shift in the threshold voltage. Two mechanisms are known to be responsible for such failure: impact ionization and trap creation. Impact ionization in the SiO2, or electron-hole pair generation, would occur when the energy of the electrons exceeds the bandgap energy of 9 eV, and these energetic electrons collide with the crystal lattice and create ions. In the trap-creation process, defects are produced by hot electrons breaking silicon-hydrogen bonds (Si-H) near the drain [248]. H+ ions created may diffuse back to the source and cause additional defects by combining with other hydrogen atoms. This H+ ion diffusion is called hydrogen effect. Mechanical stress can increase the diffusion of H atoms from passivation layers to the gate oxide [303].

Hot carrier effects have been known to cause overloading of the substrate bias generator, threshold variation due to body effect, DRAM refresh-time degradation, and in some cases, avalanche breakdown of the MOSFET. Since there is an exponential decrease in hot carriers with a decrease in supply voltage, hot carrier degradation is not expected to be a major reliability problem for DRAMs in the gigabit regime that rely on a supply voltage of less than 1 V. However, voltage overshoots can increase the likelihood of hot carrier degradation, and such overshoots can be caused by lower capacitive loads, higher transconductances [59], and the feedforward effect due to lower supply voltages [510].

1.2.5 Latchup susceptibility

Historically, CMOS was used for manufacturing SRAMs before being used on DRAMs and other memories, and latchup is a well-studied problem with CMOS devices in general. As devices are scaled down, short-channel transistors can exhibit greater susceptibility to latchup. However, latchup depends on many other process factors apart from channel length, such as epitaxial layer thickness and doping pro-file. It was found [193] that the threshold for particle-induced latchup is influenced by both the channel length and the epitaxial layer thickness. Latchup results from a parasitic bipolar action (illustrated in Chapter 3) which causes a thyristor-type P-N-P-N junction to form in a CMOS device. This phenomenon causes a chip to self-destruct by the self-sustaining latching action of the thyristor, which draws large currents from the power supply. When this happens, the power supply must be disconnected to prevent the chip from undergoing self-destruction.

Various process modifications are used to reduce the possibility of latchup, some of which are use of silicon-on-insulator (SOI) substrates, described in Chapter 3, profiling the impurity doping in the well to decrease minority carrier lifetime in the parasitic base region, use of guard rings on the wells, use of extra well contacts and more spacings, and so on.

1.2.6 Soft errors

Soft errors are intermittent or transient failures that result in loss of data but do not bring about permanent damage to the device. They are briefly reviewed here and are discussed more thoroughly in Chapter 3. These errors are found in both DRAMs and SRAMs. These errors may be produced by bit-line coupling noise or by ionization from radiation. At the terrestrial level, these errors may be caused by ground-level cosmic rays, neutrons, and alpha particles impinging on the memory device.

  1. Noise voltages: A wide range of mechanisms are known to cause noise in both SRAMs and DRAMs – for example, imbalance of the bit-line capacitances, voltage bump at the cell-plates of DRAMs, precharge voltage and storage transistor imbalances, and pattern-sensitive or coupling faults affecting bit-line pairs due to capacitive crosstalk.

    As deep-submicron processing technologies are progressively getting scaled down toward 0.07-mm feature sizes, signal integrity problems in global interconnect, such as power and global control lines, are becoming increasingly serious. In particular, the ratio of coupling to the total wire capacitance for global wires is increasing as the width of wires and the minimum distance between them are both shrinking, and the thickness is roughly constant. The large coupling capacitance can produce signal interference, especially as clock rates and signal edge rates increase. These problems are even worse as the interconnect density increases, for example, for systems-on-a- chip (SoCs). Ground bounce caused by higher currents and edge rates diminishes the noise margin of logic gates. Higher resistance of interconnect is also a major factor in causing large voltage drops that contribute to noise. Furthermore, scaled down power supply and threshold voltages produce lower noise margins for logic gates, and use of dynamic logic in high-performance circuits contributes to even lower noise immunity. Twisted bit-line architectures of DRAMs have certain advantages in eliminating some types of coupling noise. Sometimes, undesirable charge injection from substrate-bias generators may also lead to noise.

  2. Single-event effects: Single-event effects may bring about loss of data in memory devices used in terrestrial and space applications without necessarily causing permanent damage. As described in Chapter 3, such phenomena are called soft errors or single-event upsets (SEUs). These effects are produced by ionizing radiation that may originate from outer space or from the chip itself. Radioactive decay within the package, and/or traces of thorium and uranium found in the metal and the oxide passivation layers, may produce alpha particles and other heavy ions that can cause soft errors. In some cases, single-event effects may cause permanent damage to the device, such as gate rupture (SEGR) and burnout (SEB).

    Several techniques are used to help protect against soft errors. Many manufacturers apply a wafer coating or a chip coating to absorb alpha radiation. Alternatively, or additionally, the capacitance of a storage cell can be increased to absorb the particle-induced charge without switching the stored state. A 50-fF capacitor charged to 1 V above or below the bit line would transfer 50 fC of charge to or from the bit line. This corresponds to about 300,000 electrons and is approximately the minimum signal that can withstand an alpha-particle impact. Nowadays, DRAMs use deep trench-type and stacked capacitors for increased capacitance. Gate oxide thicknesses can be scaled down, or gate material with a higher dielectric constant than that of silicon dioxide, such as silicon nitride, may be used for increased immunity to soft errors. Another approach is to use a nonvolatile ferroelectric storage capacitor which uses a dielectric with a very high dielectric constant and stays polarized by an electric field, until the polarization is reversed by an opposite field.

    From the process scaling standpoint, voltage scaling and higher substrate doping concentrations together work to reduce charge collection and consequently, to decrease the likelihood of soft errors [354]. The relationship Charge collected normalized to 64M between charge collected normalized to 64-Mb DRAM generation and the channel length is shown in Figure 1.2. It shows two plots, one with only voltage scaling, and the other with voltage scaling and increase in substrate dopant concentration. It is found that voltage scaling and increased dopant concentration work synergistically to increase the soft error immunity.

    Figure 1.2Figure 1.2. Charge collected due to an alpha particle hit, normalized to the 64 Mb DRAM generation; courtesy [227]. Reprinted from Microelectronics Reliability, vol. 37, no. 1, W.H. Krautschneider, A. Kohlhase, and H. Terletzki, "Review Paper: Scaling Down and Reliability Problems of Gigabit CMOS Circuits," pp. 19-37, © 1997, with permission from Elsevier Science Ltd.

    Besides the above, some CMOS processes, such as those that use epitaxial layers or silicon-on-insulator (SOI) substrates, may exhibit some natural immunity to ionizing radiation. These processing techniques are described in Chapter 3.

Ionizing radiation such as alpha particles penetrate the die surface and create a track of electron-hole pairs. In DRAM cells, the storage capacitances, such as trench-type capacitances, can collect sufficient numbers of these minority carriers to change the state of the cells. To mitigate such problems, one solution is to have the DRAM storage capacitor inside the trench instead of on the outside. In SRAM cells, energetic particle impacts can cause the high node of the cross-coupled inverter pair to be discharged and the recovery process to be slower than the feedback through the inverter on the other side, causing the cell to change states. Such particles typically cause most of their damage (i.e., discharging of storage nodes) within 5 to 10 ps of impact. Since the PMOS load devices in modern-day SRAMs are usually very weak and may take 25 to 50 ps to restore the lost charge, SRAM devices are also quite susceptible to soft errors. The mechanism for SRAM upsets due to ionization radiation is detailed in Chapter 3.

The failure rate for soft errors, called the soft error rate (SER) is measured in 'failures in time' (FITs), where 1000 FITs = 1000 failures in 109 device hours.

In a DRAM chip more than 98% of the failures that occur during the normal operation are radiation-induced soft errors, [268, 290, 381]. Online hard and medium errors (errors that may not be permanent but are difficult to correct, like pattern-sensitive and coupling faults) are relatively infrequent in a well-designed chip. A small fraction of failures are due to transients such as voltage spikes and man-made statics. By introducing suitable filtering circuits, these sources of transient errors can be suppressed sufficiently. But radiation-induced soft errors become increasingly critical as cell dimensions are scaled down. The capacitor value and the cell topography play an important role in determining the soft error rate (SER). The memory plane of a DRAM chip is most sensitive to upsets caused by particle hits. The peripheral logic and decoder are usually robust to ionizing radiation and very rarely contribute to soft errors. Moreover, such errors can be easily corrected by data retry since the intermittent faults in such circuits are usually combinational. The two most sensitive structures in a DRAM plane are storage cells and bit lines. The soft failure modes in DRAMs are described briefly below, and are reviewed again in Chapter 3.

  1. Storage cell and bit-line mode errors: A DRAM storage cell is a very tiny capacitor (a few fF) that can easily be discharged by ions created by energetic particles (such as alpha) penetrating the device. The planar capacitors used in the past were the most vulnerable to such upsets. Trench and stacked capacitors and their variations have greater immunity to these upsets, as explained in Chapter 3.

    Let us recall the organization of a DRAM chip to understand bit-line-mode soft error. As shown in Figure 1.3, a typical DRAM utilizes a differential amplifier for sensing the voltage difference between a pair of bit lines. One of the bit lines is attached to a regular cell and the other to a dummy cell. There is one dummy cell for every memory partition. Data are stored in capacitors at crosspoints of different bit lines and word lines. A memory cell typically consists of a storage capacitor in series with an access transistor that is selected by the word line connected to its gate. The dummy cell, also known as a reference cell, stores a fixed charge QR.

    Figure 1.3Figure 1.3. A typical DRAM organization; courtesy [462] © 1982 IEEE

    A cell is said to contain a 1 if its capacitor stores a charge QC ≥ QR; otherwise, it is said to contain a 0. A cell can be read by sensing its stored charge through the bit line and the differential sense amplifier. A read cycle consists of two distinct phases: the precharge phase and the sense phase. During the precharge phase, both bit lines are charged to a predetermined level VP , which is typically half the supply voltage. After precharging, both bit lines remain in a floating state. When a cell is selected for a read operation, the two word lines are activated simultaneously to select the reference cell. Charge sharing happens between the selected cell and its bit line, and between the dummy cell and its bit line. The voltage difference V between the two bit lines after this charge-sharing process is sensed to read the value of the selected cell. If V is positive (negative) and is greater in magnitude than the differential threshold voltage vth, then the selected cell is recognized to have a 1(0). If V is smaller in magnitude than vth, the selected cell may be read incorrectly by the sense amplifier.

    The bit line is vulnerable to soft errors during the sensing phase, particularly in the interval from the start of the sensing phase to sense amplifier latchup when the bit line remains floating. During this phase, if a particle strike causes charge to be collected on the bit line containing the reference cell, its charge may be reduced resulting in a new, lower reference voltage V R. If the selected cell contains a 0, then the voltage difference V may become less than vth causing a faulty read operation. This is shown in the second plot of Figure 1.4. On the other hand, if during the sensing phase, the particle causes charge to be transferred to the bit line containing the selected cell (storing a 1), the bit-line voltage may degrade such that the magnitude of V is less than vth. The resulting read operation would also be erroneous, as shown in the last plot of Figure 1.4.

    Figure 1.4Figure 1.4. Bit-line mode soft error due to alpha particles; courtesy [280] © 1993 IEEE

  2. Charge-sharing and multibit errors: In the 1980s and early 1990s, the kind of DRAM array organizations commonly used were such that if ionizing radiation (such as alpha particles) was incident on the intervening space between two adjoining trench capacitors, the resulting plasma discharge might delete data in both capacitors [280] and cause a double-bit error on the same word.

This is illustrated in Figure 1.5. Chern et al. [68] have done extensive Monte Carlo simulation to study the charge sharing mechanism due to alpha-particle-induced plasma short between capacitors. Their study strongly indicated that trench capacitors are likely to suffer from double-bit upsets. The Monte Carlo simulation done by Sai-Halasz et al. [381], has indicated that as the feature width is reduced and the critical charge in storage capacitors decreases, double-bit soft errors will tend to dominate over single-bit errors. It may be emphasized that the earlier soft-error analysis techniques were based on a single-event upset where the storage capacitors were planar. Therefore, conventional on-chip and system-level error-correcting circuits of the single-error correcting, double-error detecting (SEC-DED) type were found unsuitable for correcting the double-bit upsets described above. With the increasing popularity of column-multiplexed addressing and one-bit-per-subarray schemes in the 1990s (described in greater detail in Chapters 3 and 6), double-bit errors in the same memory word due to single events have become virtually nonexistent because bits of the same word are typically very far apart in the array. However, a pair of independent single events may cause a double-bit error in a memory word. Also, an impinging ion at a near-grazing incidence may have a large upset track length (due to closely spaced junctions with scaled-down feature size). The upset track length is the number of adjacent memory bits that are affected by the particle strike. Such large upset track lengths may have a slight chance of causing a double-bit upset, particularly if the degree of column multiplexing is low (i.e., subarrays are very narrow and have few columns).

Figure 1.5Figure 1.5. Double-bit soft errors in three-dimensional DRAM cells

1.2.7 Electrostatic discharge and electrical overstress

Electrostatic discharge (ESD) and electrical overstress (EOS) may originate from static electricity produced by the human body, from poorly grounded equipment, or from the environment, and may lead to breakdown of the thin gate oxide layer.

The critical dielectric field strength (dc) required for breakdown of SiO2 is about 10 MV/cm, and these fields are much higher under pulsed conditions [6,130]. Therefore, the breakdown voltage decreases with decreasing thickness of SiO2. For a 0.25-mm NMOS transistor with a gate oxide thickness of 7 nm, the pulsed breakdown voltage will be 14 to 15 V [6].

As MOSFETs have become more sensitive to ESD in recent years, on-chip ESD protection circuitry at the I/O pins are necessary to protect memory devices from high-voltage spikes. Since process technologies have rapidly advanced to include thinner gate oxides, shallower junctions, lightly doped drain (LDD) or graded drain junctions, silicide-clad diffusion, and multiple metal layers, protection circuit requirements have also evolved significantly [108] from the simple voltage-clamping diodes that were used in the past.

The main requirements of an ESD protection device are small area and the ability to turn on quickly to conduct a large amount of current in a very short time. Among the various ESD protection devices, silicon-controlled rectifiers (SCRs) [62, 326] have been very popular, since they offer the maximum ESD protection while occupying the smallest silicon area [74, 105]. An SCR is a lateral thyris-tor [62] that triggers at a specific breakdown voltage (called Vtrig, the triggering voltage) and conducts an ESD current to ground through a parasitic, low-resistance bipolar path. This conduction mechanism is quite similar to latchup. In the past, SCRs exhibited an increased triggering voltage, which limited their use only in input pads [377]. Invention of the low-voltage triggering SCR (LVTSCR) [62] permitted the use of SCRs at output and power supply pads which are vulnerable to much smaller ESD voltage spikes. The triggering voltage of SCRs affects the safety and reliability of sensitive internal buffers of integrated circuits. Approaches used to further decrease the triggering voltage include gate-coupled LVTSCR [207] and P-well coupling to ESD stressed pads [326] based on the ability to bias the P-well independently in triple-well CMOS technologies. It should be noted that the shorter channel lengths and decreasing feature sizes in deeper submicron technologies actually favor the parasitic bipolar mechanism by decreasing the avalanche breakdown voltage [6] and cause improved ESD protection.

However, shallow junctions produced by scaling down of process technology leads to an increase in the vulnerability to voltage spikes during ESD events [107]. This necessitates the use of metal TiW barriers in the contacts and new contact filling techniques and materials to control the problem of contact melting. Also, to minimize leakage current after ESD stress, ESD protection with forward-biased diodes and large shunting NMOS transistors, instead of with avalanching junctions, is examined in [294,501].

Furthermore, as scaling progresses, there is a trend toward higher pad counts of complex chips. This trend results in a diminishing pad-to-pad pitch (of 50 to 80 mm) with modern packages such as BGA (ball grid array). Therefore, the area available for the ESD pad protection devices is reduced significantly. Larger chip sizes also have longer power lines with high parasitic resistance, causing large voltage drops and increased ESD vulnerability of the internal circuitry beyond the ESD protection circuitry [106, 451]. Also, multiple power busses in highly complex gigabit memory circuits would need to have their own pins to the external power supply (to avoid noise problems) and would also require internal clamping devices between the various power supplies and ground [6,251,479].

1.2.8 Metallization reliability

Electromigration, stress migration, and metal contamination with radioactive elements such as uranium and thorium, comprise the well-known metallization reliability problems in deep submicron technologies. Radioactive contamination of metal lines can cause single-event effects that are described in Chapter 3. Electro-migration and stress migration are described in the following sections.


Electromigration is a phenomenon in which metal atoms are moved by a large current in metal interconnects, for example, in power supply lines. When metal ions collide with the current of scattering electrons, the momentum transfer between electrons and metal ions moves the metal ions in the direction of the electron wind. The result is the generation of voids (centers of negative charge) and hillocks and whiskers (centers of positive charge). The process is unstable, as high current density leads to the creation of voids, which further increases the current density.

As scaling progresses, drain saturation currents of MOSFETs will increase only moderately [181] due to the significant reduction of the effective gate voltage (VGS - Vth) resulting from the lower supply voltage. Therefore, at first glance, one would expect that such a small increase in the drain current may not represent a serious electromigration problem with metal lines carrying this current. However, the presence of grain boundaries across the Al line width (for sub-0.25-mm technologies) may cause localized regions of increased current density and electromigration vulnerability. Techniques that have been found to be very successful in achieving much improved electromigration resistance include – (1) use of sandwich layers, such as Ti/W/AlSi [170, 440] and TiN/Al(Si)Cu/TiN, which causes better electromigration resistance at the expense of a higher resistivity in the interconnects; (2) better global planarization techniques, such as CMP (chemical mechanical polishing); (3) better contact at vias and plugs, for example, with tungsten [198] and dual damascene [199]; and (4) use of Cu interconnects, which have lower sheet resistance and higher melting temperature than Al, thereby improving the electro-migration lifetime by an order of magnitude [16,143,467].

Stress migration

Stress migration represents another reliability problem with the metallization for scaled-down technologies. Stress migration is interfacial mechanical stress that causes the diffusion of metal ions and the creation of voids. It is not independent of electromigration [175]. Stress migration is caused by the mismatch between the thermal expansion coefficients of the metal line and the insulator. Sub-0.25-mm Al lines are very vulnerable to creep voiding [440] because of the grain boundaries across the entire line width [175]. To minimize interfacial stress, the interlayer dielectric (ILD) in metal lines and the deposition method must be selected appropriately. Some techniques to minimize electromigration will also reduce stress migration and improve reliability. Examples of such techniques are: layered interconnect structures, such as TiN/Al(Si)Cu/TiN [209, 265], pure refractory metal lines such as tungsten [157,230], and better global planarization, for example, by using CMP (chemical mechanical polishing), and encapsulation with damascene as the ILD.

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  • With the consent of the individual (or their parent, if the individual is a minor)
  • In response to a subpoena, court order or legal process, to the extent permitted or required by law
  • To protect the security and safety of individuals, data, assets and systems, consistent with applicable law
  • In connection the sale, joint venture or other transfer of some or all of its company or assets, subject to the provisions of this Privacy Notice
  • To investigate or address actual or suspected fraud or other illegal activities
  • To exercise its legal rights, including enforcement of the Terms of Use for this site or another contract
  • To affiliated Pearson companies and other companies and organizations who perform work for Pearson and are obligated to protect the privacy of personal information consistent with this Privacy Notice
  • To a school, organization, company or government agency, where Pearson collects or processes the personal information in a school setting or on behalf of such organization, company or government agency.


This web site contains links to other sites. Please be aware that we are not responsible for the privacy practices of such other sites. We encourage our users to be aware when they leave our site and to read the privacy statements of each and every web site that collects Personal Information. This privacy statement applies solely to information collected by this web site.

Requests and Contact

Please contact us about this Privacy Notice or if you have any requests or questions relating to the privacy of your personal information.

Changes to this Privacy Notice

We may revise this Privacy Notice through an updated posting. We will identify the effective date of the revision in the posting. Often, updates are made to provide greater clarity or to comply with changes in regulatory requirements. If the updates involve material changes to the collection, protection, use or disclosure of Personal Information, Pearson will provide notice of the change through a conspicuous notice on this site or other appropriate way. Continued use of the site after the effective date of a posted revision evidences acceptance. Please contact us if you have questions or concerns about the Privacy Notice or any objection to any revisions.

Last Update: November 17, 2020