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1.5 References

1. J. E. Lilienfeld, U.S. Patent 1,745,175 (1930).

2. O. Heil, U.S. Patent 439,457 (1935).

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17. The National Technology Roadmap for Semiconductor, SIA Handbook, 1997.

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24. E. Musoll et al., "Working-Zone Encoding for Reducing the Energy in Microprocessor Address Busses," IEEE Trans. VLSI Syst., Vol. 6, No. 12, pp. 568–572, Dec. 1998.

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27. M. Hiraki et al., "Data Dependent Logic Swing Internal Bus Architecture for Ultra Low-Power LSI's," IEEE J. Solid State Circuits, Vol. 30, No. 4, pp. 397–402, April 1995.

28. H. Yamauchi et al., "An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultra-High Data Rate ULSI's," IEEE J. Solid-State Circuits, Vol. 30, No. 4, pp. 423–431, April 1995.

29. R. Colsham and B. Jaroun, "A Novel Reduced Swing CMOS BUS Interface Circuit for High-Speed Low-Power VLSI Systems," Proc. IEEE Intl. Symp. Circuits and Systems, Vol. 4, pp. 351–354, May 1994.

30. J. Rabaey, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, N.J., 1996.

31. T. Burd, "Energy Efficient Processor System Design," Ph.D. dissertation, Univ. Calif., Berkeley, 1998.

32. G. Shahidi et al., "Partially-Depleted SOI Technology for Digital Logic," Proc. IEEE Int. Solid-State Circuits Conf., pp. 426–427, Feb. 1999.

33. H. S. P. Wong, D. J. Frank, P. M. Solomon, C. H. J. Wann, and J. J. Welser, "Nanoscale CMOS," Proc. of IEEE, Vol. 87, No. 4, pp. 537–570, April 1999.

34. Y. Taur, C. H. Wann, and D. J. Frank, "25-nm CMOS Design Considerations," IEEE IEDM Tech. Dig., pp. 789–792, 1998.

35. J. H. Stathis and D. J. DiMaria, "Reliability Projection for Ultra-Thin Oxides at Low Voltage," IEEE IEDM Tech. Dig., pp.167–170, 1998.

36. M. T. Bohr, "Interconnect Scaling—The Real Limiter to High Performance ULSI," IEEE IEDM Tech. Dig., pp. 241–244, Dec. 1995.

37. D. Pramanik, "Aluminum-Based Metallurgy for Global Interconnects," MRS Bulletin, Metallization for Integrated Circuit Manufacturers, Vol. XX, No. 11, pp. 57–60, Nov. 1995.

38. R. L Jackson, E. Broadbent, T. Cacouris, A. Harrus, M. Biberger, E. Patton, and T. Welsh, "Processing and Integrations of Copper Interconnects," Damascus Technical Paper, Novellus homepage (http://www.damascus.novellus.com damascus/index.htm), Novellus Systems, San Jose. Calif.

39. R. Mehra et al., "A Partitioning Scheme for Optimizing Interconnect Power," IEEE J. Solid-State Circuits, Vol. 32, No. 3, pp. 433–443, March 1997.

40. E. De Man and M. Schobinger, "Power Dissipation in the Clock System of Highly Pipelined ULSI CMOS Circuits," 1994 International Workshop on Low Power Design, pp. 133–138, April 1994.

41. D. Liu and C. Svensson, "Power Consumption Estimation in CMOS VLSI Chips," IEEE J. Solid-State Circuits, Vol. 29, No. 6, pp. 663–670, June 1994.

42. H. J. Chao and C. Johnston, "Behaviour Analysis of CMOS Flip-Flops," IEEE J. Solid-State Circuits, Vol. 24, No. 5, pp. 1454–1458, Oct. 1989.

43. S. S. Rofail and K. S. Yeo, Low-Voltage, Low-Power Digital BiCMOS Circuits: Circuit Design, Comparative Study and Sensitivity Analysis, Prentice Hall, Upper Saddle River, N.J., 2000.

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