Low-Power Design: An Overview
The history of semiconductor devices began in the 1930s, when Lilienfeld and Heil [1,2] first proposed the Metal Oxide Semiconductor (MOS) Field-Effect Transistor (FET). However, it took 30 years before this idea was applied to functioning devices to be used in practical applications , and, up to the late 1970s, bipolar devices were the mainstream digital technology. Around 1980, this trend took a turn when MOS technology caught up and there was a crossover between bipolar and MOS shares. Complementary-MOS (CMOS) was finding more widespread use due to its low power dissipation, high packing density, and simple design, such that, by 1990, CMOS covered more than 90% of the total MOS sales, and the relation between MOS and bipolar sales was two to one.
In digital circuit applications, there was a performance gap between CMOS and bipolar logic. The existence of this gap, as shown in Figure 1.1, implies that neither CMOS nor bipolar had the flexibility required to cover the full delay-power space. This flexibility was achieved with the emergence of bipolar-compatible CMOS (BiCMOS) technology, the objective of which is to combine bipolar and CMOS so as to exploit the advantages of both at the circuit and system levels.
Fig. 1.1 A comparison of CMOS, bipolar, and BiCMOS technologies in terms of speed and power.
In 1983, a bipolar-compatible process based on CMOS technology was developed, and BiCMOS technology with both the MOS and bipolar devices fabricated on the same chip was developed and studied . The principal BiCMOS circuit in the early days was the BiCMOS totem-pole gate  as shown in Figure 1.2. This circuit was proposed by Lin et al. and is one of the earliest versions to be used in practice. It is commonly referred to as the conventional BiCMOS circuit. Since 1985, BiCMOS technologies developed beyond initial experimentation to become widespread production processes. The state-of-the-art bipolar and CMOS structures have been converging. Today, BiCMOS has become one of the dominant technologies used for high-speed, low-power, and highly functional Very-Large-Scale-Integration (VLSI) circuits , especially when the BiCMOS process has been enhanced and integrated into the CMOS process without any additional steps . Because the process steps required for both CMOS and bipolar are similar, these steps can be shared for both of them.
The concern for power consumption has been part of the design process since the early 1970s. At that time, however, the main design focuses were providing for high-speed operation and a design with minimum area; design tools were all geared toward achieving these two goals. Since the early 1990s, the semiconductor industry has witnessed an explosive growth in the demand and supply of portable systems in the consumer electronics market. High-performance portable products, ranging from small hand-held personal communication devices, such as pagers and cellular phones, to larger and more sophisticated products that support multimedia applications, such as lap-top and palm-top computers, have enjoyed considerable success among consumers. Indeed, we anticipate that, in the near future, almost half of the consumer electronics market will be in portable systems. Even though the performance, support features, and cost of a portable product are important to the consumers, its portability is often a key differentiator in a user's purchase decision.
1.1 Low-Power Design: An Overview
In the past, due to a high degree of process complexity and the exorbitant costs involved, low-power circuit design and applications involving CMOS and BiCMOS technologies were used only in applications where very low power dissipation was absolutely essential, such as wrist watches, pocket calculators, pacemakers, and some integrated sensors. However, low-power design is becoming the norm for all high-performance applications, as power is the most important single design constraint. Although designers have different reasons for lowering power consumption, depending on the target application, minimizing the overall power dissipation in a system has become a high priority.
One of the most important reasons for this trend is the advent of portable systems. As the "on the move with anyone, anytime, and anywhere" era becomes a reality, portability becomes an essential feature of the electronic systems interfacing with nonelectronic systems, emphasizing efficient use of energy as a major design objective.
The considerations for portability are due to numerous factors. First, the size and weight of the battery pack is fundamental. A portable system that has an unreasonably heavy battery pack is not practical and restricts the amount of battery power that can be loaded at any one time. Second, the convenience of using a portable system relies heavily on its recharging interval. A system that requires frequent recharging is inconvenient and hence limits the user's overall satisfaction in using the product.
Although the battery technology has improved over the years, its capacity has only managed to increase by a factor of two to four in the last 30 years or so; the computational power of digital integrated circuits has increased by more than four orders of magnitude. To illustrate the importance of low-power design, or the lack of it in portable systems, consider a future portable multimedia terminal that supports high-bandwidth wireless communication; bi-directional motion video; high-quality audio, speech, and pen-based input; and full texts/graphics. The power of such a terminalwhen implemented using off-the-shelf components not designed for low poweris projected to reach approximately 40 W. Based on the current Nickel-Cadmium (NiCd) battery technology, which offers a capacity of 20 W-hour/pound, a 20-pound battery pack is required to stretch the recharge interval to 10 hours. Even with new battery technologies, such as the rechargeable lithium or polymers, battery capacity is not expected to improve by more than 30 to 40% over the next 5 years. Hence, in the absence of low-power design techniques, future portable products will have either unreasonably heavy battery packs or a very short battery life.
The issue of power also embraces reliability and the cost of manufacturing nonportable high-end applications. The rapidly increasing packing density, clock frequency, and computational power of microprocessors have inevitably resulted in rising power dissipation. The trends relating to the power consumption of microprocessors indicate that power has increased almost linearly with area-frequency product over the years. For example, the DEC21164, which has a die area of 3 cm2 and runs on a 300-MHz clock frequency, dissipates as much as 50 W of power. Such high power consumption requires expensive packaging and cooling techniques given that insufficient cooling leads to high operating temperatures, which tend to exacerbate several silicon failure mechanisms. To maintain the reliability of their products, and avoid expensive packaging and cooling techniques, manufacturers are now under strong pressure to control, if not reduce, the power dissipation of their products.
Finally, due to the increasing percentage of electrical energy usage for computing and communication in the modern workplace, low-power design is in line with the increasing global awareness of environmental concerns. As a result, power has emerged as one of the most important design and performance parameters for integrated circuits. Only a few years ago, the power dissipation of a circuit was of secondary importance to such design issues as performance and area. The performance of a digital system is usually measured only in terms of the number of instructions it can carry out in a given amount of time, that is, its throughput. The area required to implement a circuit is also important as it is directly related to the fabrication cost of the chip. Larger die areas lead to more expensive packaging and lower fabrication yield. Both effects translate to higher cost. Because the performance of a system is usually improved at the expense of silicon area, a major task for integrated chip (IC) designers in the past was to achieve an optimal balance between these two often-conflicting objectives. Now, with the rising importance of power, this balance is no longer sufficient. Today, IC designers must design circuits with low-power dissipation without severely compromising the circuits' performance.
Clearly, power has become a major consideration in VLSI and giga-scale-integration (GSI) engineering due to portability, reliability, cost, and environmental concerns. The BiCMOS technology that combines the low-power dissipation and high packing density of CMOS with the high-speed and high-output drive of bipolar devices has proven to be an excellent workhorse for portable as well as nonportable applications. For many years to come, device miniaturization together with the search for even lower power and lower voltage requirements will continue. To cater to such an ever-increasing demand, the CMOS/BiCMOS technology shall be the answer.