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  1. 1.1 Signal Integrity Analysis Trends
  2. 1.2 Challenges of High-Speed Signal Integrity Design
  3. 1.3 Organization of This Book
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1.2 Challenges of High-Speed Signal Integrity Design

This section provides detailed descriptions of a number of the challenges facing signal-integrity (SI) engineers during high-speed SI design.

One challenge is that system-design methodology must change so that SI concerns are accounted for during the architecture phase, rather than later in the process. This issue is more pronounced for designs moving into high data rates. In the past, engineers have relied on their own experience until something goes wrong. This can be very costly in terms of product delay and returns.

SI engineers also need to identify the critical timing and voltage parameters and relationships of the design. Having a good understanding of the signaling methods and clocking architecture is critically important. Not all SI engineers will have the opportunity to work on a new signaling method; most engineers typically work with a standard defined by industry consortium. Even in this case, the SI engineer needs to understand how signaling functions and its key requirements. Identifying worst-case scenarios is also crucial.

SI engineers must be able to build accurate models for passive interconnect as well, including the package, PCB, and connectors. These models must capture frequency dependent loss, crosstalk, and reflections. They must also capture 3D, as well as full-wave effects. These models can be used in either time-domain or frequency-domain simulations.

SI engineers must build confidence in the accuracy of the passive model by performing detailed correlation with the hardware, in both the time and frequency domains, using VNA and TDR. The impact of manufacturing tolerances must be considered for high volume productions.

SI engineers also need to build an accurate model of the power distribution network, to account for the effects of supply noise on system performance. The power distribution network must not only be appropriate for on-chip power delivery analysis (such as IR, EM, and AC supply noise); it must also be able to capture system behavior, such as coupling between signal and supply rails. The supply voltage tolerance at transistors and package pins must be defined. Bypassing requirements on-chip, on-package, and on PCB must be defined for suppressing high, medium, or low frequency supply noise.

SI engineers need to account for the effects of non-ideal circuit behavior as well, such as transmitter jitter and receiver offset and/or sensitivity. Deterministic noise sources (such as DCD or ISI), and random noise sources (due to thermal or shot noise) must be modeled. The ability of SI engineers to work in a multi-disciplinary environment is very important when accessing the risks or benefits of various design options, and when helping to define an optimal signaling architecture, in terms of both speed and power. Moreover, SI engineers must understand the relationship between supply noise and jitter for a given clocking architecture. Certain clocking architectures may be more susceptible to noise than others. Finding the noise-to-jitter transfer function is essential.

Finally, SI engineers must be able to work in the lab, using various instruments, ranging from VNA, TDR, DCA (digital sampling scope), spectrum analyzers, and BERT (bit error rate tester). One must be able to capture waveforms in the lab, correlate them with simulation, and explain the observed system behavior. Using the correlated model, one must be able to find the root cause of the failure or instability, as well as to recommend design changes for future improvements.

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