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Introduction to Power Integrity for I/O Interfaces

Oct 28, 2010

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This chapter is from the book 

Power Integrity for I/O Interfaces: With Signal Integrity/ Power Integrity Co-Design

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References

1. M. Swaminathan, E. Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2007.

2. I. Novak (Executive Editor), Power Distribution Design Methodologies, IEC 2008.

3. B. Young, Digital Signal Integrity, Prentice Hall, 2001.

4. R. Bashirullah, Wentai Liu; R. Cavin III, "Delay and power model for current-mode signaling in deep submicron global interconnects," Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002, pp 513– 515.

5. D. Heidar, M. Dessouky, H.F. Ragaie, "Comparison of output drivers for high-speed serial links," ICM 2007. Internatonal Conference on Microelectronics, 2007, pp 329–332.

6. Y-J Kim, S-W Han, K-W Park, J-K Wee, J-S Kih, "Analysis of simultaneous switching noise by short-circuit current in CMOS-single ended driver," Electronic Components and Technology Conference, 2005. Proceedings. 55th, 2005, pp 1748–1751 Vol. 2.

7. J. Kho, Chooi Ian Loh; B. Krsnik, Zhe Li, Chee Seong Fong, P. Boyle, Man On Wong, "Effect of SSN-induced PDN noise on a LVDS output buffer," Applied Electromagnetics, 2007. APACE 2007. Asia-Pacific Conference on; 2007, pp 1–5.

8. Woong Hwan Ryu and Min Wang, "A Co-Design Methodology of Signal Integrity and Power Integrity," DesignCon2006, Feb 2006.

9. Jinjun Xiong and Lei He, "Full-chip multilevel routing for power and signal integrity Design," Proceedings of Automation and Test in Europe Conference and Exhibition, vol. 2, pp 1116–1121, February 2004.

10. J. Park, H. Kim, J. S. Pak, Y. Jeong, S. Baek, J. Kim, J. Lee, and J. Lee, "Noise coupling to signal trace and via from power/ground simultaneous switching noise in high speed double data rates memory module," Proceeding of EMC, vol. 2, pp 592–597, August 2004.

11. Edward K. Chan, Mauro Lai, Myoung Joon Choi, and Woong Hwan Ryu, "Concurrent Analysis of Signal-Power Integrity and EMC for High-Speed Signaling Systems," IEEE International Symposium on Electromagnetic Compatibility, 2007. EMC 2007. 9-13 July 2007 pp 1–8.

12. M.J. Choi, and V. Pandit, "SI/PI Co-Analysis for I/O Interfaces," IBIS Summit, June 2009.

13. M. J. Choi and V. Pandit, "SI/PI Co-Analysis and Linearity Indicator," IBIS Summit, Feb. 2010.

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