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1.6 Concurrent Design Methodology

Power integrity, signal integrity, and EMC design techniques are inter-related, and their interactions need to be considered. A concurrent design methodology is needed to analyze these interactions [8, 9, 10, 11]. Common mode noise always exists due to power fluctuation and ground bounce. The common mode noise is the main contributor to EMI. The co-design approach considering signal/power integrity and EMC throughout the design, as illustrated in Figure 1.11 (a), is a fundamentally more cost-effective approach compared to a crisis-management approach. If the designer anticipates interactions between signal/power integrity and EMC at the beginning of the design process, and if noise suppression is considered for one stage or subsystem at a time, the noise mitigation techniques are simpler and more straightforward. If the designer proceeds with a disregard of various interactions until the design is close to being finished, mitigation techniques become considerably more costly, less effective, and less available, as shown in Figure 1.11 (b).

Figure 1.11

Figure 1.11 Concurrent SI/PI/EMI design

The design methodology proposed in this book is a further unified solution to the co-design of signaling systems by proposing a new metric to unify power integrity and signal integrity designs. In the co-design of signal/power integrity, several sources of coupled noise need to be considered in the signaling system that can degrade the quality of a transmitted signal. As the speed and width of interfaces increase, understanding these signal impediments and designing low-cost solutions become challenging. Signals can contaminate one another through ISI, crosstalk among adjacent signals, and PDN noise. All three items and their interaction need to be closely examined within the signaling system [13]. In summary, this book presents the power integrity design techniques taking into account the effects on signal integrity.

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