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RAM Types and Performance

The speed and performance issue with memory is confusing to some because memory speed is sometimes expressed in nanoseconds (ns) and processor speed has always been expressed in megahertz (MHz) or gigahertz (GHz). Newer and faster types of memory usually have speeds expressed in MHz, thus adding to the confusion. Fortunately, you can easily translate MHz/GHz to ns, and vice versa.

A nanosecond is defined as one billionth of a second—a very short time indeed. To put some perspective on that, the speed of light is 186,282 miles (299,792 kilometers) per second in a vacuum. In one billionth of a second, a beam of light travels a mere 11.80 inches or 29.98 centimeters—less than the length of a typical ruler!

Chip and system speeds have often been expressed in megahertz (MHz), which is millions of cycles per second, or gigahertz (GHz), which is billions of cycles per second. Today's processors run in the 2GHz–4GHz range with most performance improvements coming from changes in CPU design (such as multiple cores) rather than pure clock speed increases.

Because it is confusing to speak in these different terms for speeds, I thought it would be interesting to see how they compare. Earlier in this chapter I listed formulas you could use to mathematically convert these values. Table 6.2 shows the relationship between common nanosecond (ns) and megahertz (MHz) speeds associated with PCs from yesterday to today and tomorrow.

Table 6.2. The Relationship Between Megahertz (MHz) and Cycle Times in Nanoseconds (ns)

 Clock Speed Cycle Time 4.77MHz 210ns 6MHz 167ns 8MHz 125ns 10MHz 100ns 12MHz 83ns 16MHz 63ns 20MHz 50ns 25MHz 40ns 33MHz 30ns 40MHz 25ns 50MHz 20ns 60MHz 17ns 66MHz 15ns 75MHz 13ns 80MHz 13ns 100MHz 10ns 120MHz 8.3ns 133MHz 7.5ns 150MHz 6.7ns 166MHz 6.0ns 180MHz 5.6ns 200MHz 5.0ns 225MHz 4.4ns 233MHz 4.3ns 250MHz 4.0ns 266MHz 3.8ns 300MHz 3.3ns 333MHz 3.0ns 350MHz 2.9ns 366MHz 2.7ns 400MHz 2.5ns 433MHz 2.3ns 450MHz 2.2ns 466MHz 2.1ns 500MHz 2.0ns 533MHz 1.88ns 550MHz 1.82ns 566MHz 1.77ns 600MHz 1.67ns 633MHz 1.58ns 650MHz 1.54ns 666MHz 1.50ns 700MHz 1.43ns 733MHz 1.36ns 750MHz 1.33ns 766MHz 1.31ns 800MHz 1.25ns 833MHz 1.20ns 850MHz 1.18ns 866MHz 1.15ns 900MHz 1.11ns 933MHz 1.07ns 950MHz 1.05ns 966MHz 1.04ns 1,000MHz 1.00ns 1,100MHz 0.91ns 1,133MHz 0.88ns 1,200MHz 0.83ns 1,300MHz 0.77ns 1,400MHz 0.71ns 1,500MHz 0.67ns 1,600MHz 0.63ns 1,700MHz 0.59ns 1,800MHz 0.56ns 1,900MHz 0.53ns 2,000MHz 0.50ns 2,100MHz 0.48ns 2,200MHz 0.45ns 2,300MHz 0.43ns 2,400MHz 0.42ns 2,500MHz 0.40ns 2,600MHz 0.38ns 2,700MHz 0.37ns 2,800MHz 0.36ns 2,900MHz 0.34ns 3,000MHz 0.333ns 3,100MHz 0.323ns 3,200MHz 0.313ns 3,300MHz 0.303ns 3,400MHz 0.294ns 3,500MHz 0.286ns 3,600MHz 0.278ns 3,700MHz 0.270ns 3,800MHz 0.263ns 3,900MHz 0.256ns 4,000MHz 0.250ns 4,100MHz 0.244ns 4,200MHz 0.238ns 4,300MHz 0.233ns 4,400MHz 0.227ns 4,500MHz 0.222ns 4,600MHz 0.217ns 4,700MHz 0.213ns 4,800MHz 0.208ns 4,900MHz 0.204ns 5,000MHz 0.200ns

As you can see from Table 6.2, as clock speeds increase, cycle time decreases proportionately.

Over the development life of the PC, memory has had a difficult time keeping up with the processor, requiring several levels of high-speed cache memory to intercept processor requests for the slower main memory. More recently, however, systems using DDR, DDR2, and DDR3 SDRAM have memory bus performance equaling that of the processor bus. When the speed of the memory bus equals the speed of the processor bus, main memory performance is optimum for that system.

For example, using the information in Table 6.2, you can see that the 60ns DRAM memory used in the original Pentium and Pentium II PCs up until 1998 works out to be an extremely slow 16.7MHz! This slow 16.7MHz memory was installed in systems running processors up to 300MHz or faster on a processor bus speed of 66MHz, resulting in a large mismatch between processor bus and main memory performance. However, starting in 1998 the industry shifted to faster SDRAM memory, which was able to match the 66MHz speed of the processor bus at the time. From that point forward, memory has largely evolved in step with the processor bus, with newer and faster types coming out to match any increases in processor bus speeds.

By the year 2000, the dominant processor bus and memory speeds had increased to 100MHz and even 133MHz (called PC100 and PC133 SDRAM, respectively). Starting in early 2001, double data rate (DDR) SDRAM memory of 200MHz and 266MHz become popular. In 2002, DDR memory increased to 333MHz; in 2003, the speeds increased further to 400MHz. During 2004, we saw the introduction of DDR2, first at 400MHz and then at 533MHz. DDR2 memory continued to match processor bus speed increases in PCs during 2005 and 2006, rising to 667MHz and 800MHz, respectively, during that time. By 2007, DDR2 memory was available at speeds of up to 1,066MHz, and DDR3 came on the market at 1,066MHz and faster. In 2009, DDR3 memory became the most popular memory type in new systems, with standard speeds of up to 1,600MHz. Table 6.3 lists the primary types and performance levels of PC memory.

Table 6.3. PC Memory Types and Performance Levels

 Memory Type Years Popular Module Type Voltage Max. Clock Speed Max. Throughput Single-Channel Max. Throughput Dual-Channel Max. Throughput Tri-Channel Fast Page Mode (FPM) DRAM 1987–1995 30/72-pin SIMM 5V 22MHz 177MBps N/A N/A Extended Data Out (EDO) DRAM 1995–1998 72-pin SIMM 5V 33MHz 266MBps N/A N/A Single Data Rate (SDR) SDRAM 1998–2002 168-pin DIMM 3.3V 133MHz 1,066MBps N/A N/A Rambus DRAM (RDRAM) 2000–2002 184-pin RIMM 2.5V 1,066MTps 2,133MBps 4,266MBps N/A Double Data Rate (DDR) SDRAM 2002–2005 184-pin DIMM 2.5V 400MTps 3,200MBps 6,400MBps N/A DDR2 SDRAM 2005–2008 240-pin DDR2 DIMM 1.8V 1,066MTps 8,533MBps 17,066MBps N/A DDR3 SDRAM 2008+ 240-pin DDR3 DIMM 1.5V 1,600MTps 12,800MBps 25,600MBps 38,400MBps MHz = Megacycles per second MTps = Megatransfers per second MBps = Megabytes per second SIMM = Single inline memory module DIMM = Dual inline memory module

The following sections look at these memory types in more detail.

Fast Page Mode DRAM

Standard DRAM is accessed through a technique called paging. Normal memory access requires that a row and column address be selected, which takes time. Paging enables faster access to all the data within a given row of memory by keeping the row address the same and changing only the column. Memory that uses this technique is called Page Mode or Fast Page Mode memory. Other variations on Page Mode were called Static Column or Nibble Mode memory.

Paged memory is a simple scheme for improving memory performance that divides memory into pages ranging from 512 bytes to a few kilobytes long. The paging circuitry then enables memory locations in a page to be accessed with fewer wait states. If the desired memory location is outside the current page, one or more wait states are added while the system selects the new page.

To improve further on memory access speeds, systems have evolved to enable faster access to DRAM. One important change was the implementation of burst mode access in the 486 and later processors. Burst mode cycling takes advantage of the consecutive nature of most memory accesses. After setting up the row and column addresses for a given access, using burst mode, you can then access the next three adjacent addresses with no additional latency or wait states. A burst access usually is limited to four total accesses. To describe this, we often refer to the timing in the number of cycles for each access. A typical burst mode access of standard DRAM is expressed as x-y-y-y; x is the time for the first access (latency plus cycle time), and y represents the number of cycles required for each consecutive access.

Standard 60ns-rated DRAM normally runs 5-3-3-3 burst mode timing. This means the first access takes a total of five cycles (on a 66MHz system bus, this is about 75ns total, or 5x15ns cycles), and the consecutive cycles take three cycles each (3x15ns = 45ns). As you can see, the actual system timing is somewhat less than the memory is technically rated for. Without the bursting technique, memory access would be 5-5-5-5 because the full latency is necessary for each memory transfer. The 45ns cycle time during burst transfers equals about a 22.2MHz effective clock rate; on a system with a 64-bit (8-byte) wide memory bus, this would result in a maximum throughput of 177MBps (22.2MHz x 8 bytes = 177MBps).

DRAM memory that supports paging and this bursting technique is called Fast Page Mode (FPM) memory. The term comes from the capability of memory accesses to data on the same page to be done with less latency. Most 386, 486, and Pentium systems from 1987 through 1995 used FPM memory, which came in either 30-pin or 72-pin SIMM form.

Another technique for speeding up FPM memory is called interleaving. In this design, two separate banks of memory are used together, alternating access from one to the other as even and odd bytes. While one is being accessed, the other is being precharged, when the row and column addresses are being selected. Then, by the time the first bank in the pair is finished returning data, the second bank in the pair is finished with the latency part of the cycle and is now ready to return data. While the second bank is returning data, the first bank is being precharged, selecting the row and column address of the next access. This overlapping of accesses in two banks reduces the effect of the latency or precharge cycles and allows for faster overall data retrieval. The only problem is that to use interleaving, you must install identical pairs of banks together, doubling the number of modules required.

Extended Data Out RAM (EDO)

In 1995, a newer type of DRAM called extended data out (EDO) RAM became available for Pentium systems. EDO, a modified form of FPM memory, is sometimes referred to as Hyper Page mode. EDO was invented and patented by Micron Technology, although Micron licensed production to many other memory manufacturers.

EDO memory consists of specially manufactured chips that allow a timing overlap between successive accesses. The name extended data out refers specifically to the fact that unlike FPM, the data output drivers on the chip are not turned off when the memory controller removes the column address to begin the next cycle. This enables the next cycle to overlap the previous one, saving approximately 10ns per cycle.

The effect of EDO is that cycle times are improved by enabling the memory controller to begin a new column address instruction while it is reading data at the current address. This is almost identical to what was achieved in older systems by interleaving banks of memory, but unlike interleaving, with EDO you didn't need to install two identical banks of memory in the system at a time.

EDO RAM allows for burst mode cycling of 5-2-2-2, compared to the 5-3-3-3 of standard fast page mode memory. To do four memory transfers, then, EDO would require 11 total system cycles, compared to 14 total cycles for FPM. This is a 22% improvement in overall cycling time. The resulting two-cycle (30ns) cycle time during burst transfers equals a 33.3MHz effective clock rate, compared to 45ns/22MHz for FPM. On a system with a 64-bit (8-byte) wide memory bus, this would result in a maximum throughput of 266MBps (33.3MHz x 8 bytes = 266MBps). Due to the processor cache, EDO typically increased overall system benchmark speed by only 5% or less. Even though the overall system improvement was small, the important thing about EDO was that it used the same basic DRAM chip design as FPM, meaning that there was practically no additional cost over FPM. In fact, in its heyday EDO cost less than FPM and yet offered higher performance.

EDO RAM generally came in 72-pin SIMM form. Figure 6.4 (later in this chapter) shows the physical characteristics of these SIMMs.

To actually use EDO memory, your motherboard chipset had to support it. Most motherboard chipsets introduced on the market from 1995 (Intel 430FX) through 1997 (Intel 430TX) offered support for EDO, making EDO the most popular form of memory in PCs from 1995 through 1998. Because EDO memory chips cost the same to manufacture as standard chips, combined with Intel's support of EDO in motherboard chipsets, the PC market jumped on the EDO bandwagon full force.

 See "Fifth-Generation (P5 Pentium Class) Chipsets," p. 207 and "Sixth-Generation (P6 Pentium Pro/II/III Class) Chipsets," p. 209 (Chapter 4).

EDO RAM was used in systems with CPU bus speeds of up to 66MHz, which fit perfectly with the PC market up through 1998. However, starting in 1998, with the advent of 100MHz and faster system bus speeds, the market for EDO rapidly declined, and faster SDRAM architecture became the standard.

One variation of EDO that never caught on was called burst EDO (BEDO). BEDO added burst capabilities for even speedier data transfers than standard EDO. Unfortunately, the technology was owned by Micron and not a free industry standard, so only one chipset (Intel 440FX Natoma) ever supported it. BEDO was quickly overshadowed by industry-standard SDRAM, which came into favor among PC system chipset and system designers over proprietary designs. As such, BEDO never really saw the light of production, and to my knowledge no systems ever used it.

SDRAM

SDRAM is short for synchronous DRAM, a type of DRAM that runs in synchronization with the memory bus. SDRAM delivers information in very high-speed bursts using a high-speed clocked interface. SDRAM removes most of the latency involved in asynchronous DRAM because the signals are already in synchronization with the motherboard clock.

As with any type of memory on the market, motherboard chipset support is required before it can be usable in systems. Starting in 1996 with the 430VX and 430TX, most of Intel's chipsets began to support industry-standard SDRAM, and in 1998 the introduction of the 440BX chipset caused SDRAM to eclipse EDO as the most popular type on the market.

SDRAM performance is dramatically improved over that of FPM or EDO RAM. However, because SDRAM is still a type of DRAM, the initial latency is the same, but burst mode cycle times are much faster than with FPM or EDO. SDRAM timing for a burst access would be 5-1-1-1, meaning that four memory reads would complete in only eight system bus cycles, compared to 11 cycles for EDO and 14 cycles for FPM. This makes SDRAM almost 20% faster than EDO.

Besides being capable of working in fewer cycles, SDRAM is also capable of supporting up to 133MHz (7.5ns) system bus cycling. Most PC systems sold from 1998 through 2002 included SDRAM memory.

SDRAM is sold in DIMM form and is normally rated by clock speed (MHz) rather than cycling time (ns), which was confusing during the initial change from FPM and EDO DRAM. Figure 6.5 (later in this chapter) shows the physical characteristics of DIMMs.

To meet the stringent timing demands of its chipsets, Intel created specifications for SDRAM called PC66, PC100, and PC133. For example, you would think 10ns would be considered the proper rating for 100MHz operation, but the PC100 specification promoted by Intel calls for faster 8ns memory to ensure all timing parameters could be met with sufficient margin for error.

In May 1999, the Joint Electron Device Engineering Council (JEDEC) created a specification called PC133. It achieved this 33MHz speed increase by taking the PC100 specification and tightening up the timing and capacitance parameters. The faster PC133 quickly caught on for any systems running a 133MHz processor bus. The original chips used in PC133 modules were rated for exactly 7.5ns or 133MHz; later ones were rated at 7.0ns, which is technically 143MHz. These faster chips were still used on PC133 modules, but they allowed for improvements in column address strobe latency (abbreviated as CAS or CL), which somewhat improves overall memory cycling time.

Table 6.4 shows the timing, rated chip speeds, and standard module speeds for various SDRAM DIMMs.

Table 6.4. SDRAM Timing, Actual Speed, and Rated Speed

 Timing Rated Chip Speed Standard Module Speed 15ns 66MHz PC66 10ns 100MHz PC66 8ns 125MHz PC100 7.5ns 133MHz PC133 7.0ns 143MHz PC133

SDRAM normally came in 168-pin DIMMs, running at several different speeds. Table 6.5 shows the standard single data rate SDRAM module speeds and resulting throughputs.

Table 6.5. JEDEC Standard SDRAM Module (168-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) PC66 10ns 66 1 66 8 533 PC100 8ns 100 1 100 8 800 PC133 7ns 133 1 133 8 1,066 MTps = Megatransfers per second MBps = Megabytes per second ns = Nanoseconds (billionths of a second) DIMM = Dual inline memory module
 See "SIMMs, DIMMs, and RIMMS," p. 397 (this chapter).

Some module manufacturers sold modules they claimed were "PC150" or "PC166," even though those speeds did not exist as official JEDEC or Intel standards, and no chipsets or processors officially supported those speeds. These modules actually used hand-picked 133MHz rated chips that could run overclocked at 150MHz or 166MHz speeds. In essence, PC150 or PC166 memory was PC133 memory that was tested to run at overclocked speeds not supported by the original chip manufacturer. This overclockable memory was sold at a premium to enthusiasts who wanted to overclock their motherboard chipsets, thereby increasing the speed of the processor and memory bus.

DDR SDRAM

Double data rate (DDR) SDRAM memory is a JEDEC standard that is an evolutionary upgrade in which data is transferred twice as quickly as standard SDRAM. Instead of doubling the actual clock rate, DDR memory achieves the doubling in performance by transferring twice per transfer cycle: once at the leading (falling) edge and once at the trailing (rising) edge of the cycle (see Figure 6.2). This effectively doubles the transfer rate, even though the same overall clock and timing signals are used.

DDR SDRAM first came to market in the year 2000 and was initially used on high-end graphics cards because there weren't any motherboard chipsets to support it at the time. DDR finally became popular in 2002 with the advent of mainstream supporting motherboards and chipsets. From 2002 through 2005, DDR was the most popular type of memory in mainstream PCs. DDR SDRAM uses a DIMM module design with 184 pins. Figure 6.6 (later in this chapter) shows the 184-pin DDR DIMM.

DDR DIMMs come in a variety of speed or throughput ratings and normally run on 2.5 volts. They are basically an extension of the standard SDRAM DIMMs redesigned to support double clocking, where data is sent on each clock transition (twice per cycle) rather than once per cycle as with standard SDRAM. To eliminate confusion with DDR, regular SDRAM is often called single data rate (SDR). Table 6.6 compares the various types of industry-standard DDR SDRAM modules. As you can see, the raw chips are designated by their speed in megatransfers per second, whereas the modules are designated by their approximate throughput in megabytes per second.

Table 6.6. JEDEC Standard DDR Module (184-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) PC1600 DDR200 100 2 200 8 1,600 3,200 PC2100 DDR266 133 2 266 8 2,133 4,266 PC2700 DDR333 166 2 333 8 2,667 5,333 PC3200 DDR400 200 2 400 8 3,200 6,400 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

The major memory chip and module manufacturers normally produce parts that conform to the official JEDEC standard speed ratings. However, to support overclocking, several memory module manufacturers purchase unmarked and untested chips from the memory chip manufacturers, then independently test and sort them by how fast they run. These are then packaged into modules with unofficial designations and performance figures that exceed the standard ratings. Table 6.7 shows the popular unofficial speed ratings I've seen on the market. Note that because the speeds of these modules are beyond the standard default motherboard and chipset speeds, you won't see any advantage to using them unless you are overclocking your system to match.

Table 6.7. Overclocked (non-JEDEC) DDR Module (184-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) PC3500 DDR433 216 2 433 8 3,466 6,933 PC3700 DDR466 233 2 466 8 3,733 7,466 PC4000 DDR500 250 2 500 8 4,000 8,000 PC4200 DDR533 266 2 533 8 4,266 8,533 PC4400 DDR550 275 2 550 8 4,400 8,800 PC4800 DDR600 300 2 600 8 4,800 9,600 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

The bandwidths listed in these tables are per module. Most chipsets that support DDR also support dual-channel operation—a technique in which two matching DIMMs are installed to function as a single bank, with double the bandwidth of a single module. For example, if a chipset supports standard PC3200 modules, the bandwidth for a single module would be 3,200MBps. However, in dual-channel mode, the total bandwidth would double to 6,400MBps. Dual-channel operation optimizes PC design by ensuring that the CPU bus and memory bus both run at exactly the same speeds (meaning throughput, not MHz) so that data can move synchronously between the buses without delays.

DDR2 SDRAM

DDR2 is simply a faster version of DDR memory: It achieves higher throughput by using differential pairs of signal wires to allow faster signaling without noise and interference problems. DDR2 is still double data rate, just as with DDR, but the modified signaling method enables higher clock speeds to be achieved with more immunity to noise and crosstalk between the signals. The additional signals required for differential pairs add to the pin count—DDR2 DIMMs have 240 pins, which is more than the 184 pins of DDR. The original DDR specification officially topped out at 400MHz (although faster unofficial overclocked modules were produced), whereas DDR2 starts at 400MHz and goes up to an official maximum of 1,066MHz. Table 6.8 shows the various official JEDEC-approved DDR2 module types and bandwidth specifications.

Table 6.8. JEDEC Standard DDR2 Module (240-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) PC2-3200 DDR2-400 200 2 400 8 3,200 6,400 PC2-4200 DDR2-533 266 2 533 8 4,266 8,533 PC2-5300 DDR2-667 333 2 667 8 5,333 10,667 PC2-6400 DDR2-800 400 2 800 8 6,400 12,800 PC2-8500 DDR2-1066 533 2 1066 8 8,533 17,066 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

The fastest official JEDEC-approved standard is DDR2-1066, which is composed of chips that run at an effective speed of 1,066MHz (really megatransfers per second), resulting in modules designated PC2-8500 having a bandwidth of 8,533MBps. However, just as with DDR, many of the module manufacturers produce even faster modules designed for overclocked systems. These are sold as modules with unofficial designations and performance figures that exceed the standard ratings. Table 6.9 shows the popular unofficial speed ratings I've seen on the market. Note that because the speeds of these modules are beyond the standard default motherboard and chipset speeds, you won't see any advantage to using these unless you are overclocking your system to match.

Table 6.9. Overclocked (non-JEDEC) DDR2 Module (240-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) PC2-6000 DDR2-750 375 2 750 8 6,000 12,000 PC2-7200 DDR2-900 450 2 900 8 7,200 14,400 PC2-8000 DDR2-1000 500 2 1000 8 8,000 16,000 PC2-8800 DDR2-1100 550 2 1100 8 8,800 17,600 PC2-8888 DDR2-1111 556 2 1111 8 8,888 17,777 PC2-9136 DDR2-1142 571 2 1142 8 9,136 18,272 PC2-9200 DDR2-1150 575 2 1150 8 9,200 18,400 PC2-9600 DDR2-1200 600 2 1200 8 9,600 19,200 PC2-10000 DDR2-1250 625 2 1250 8 10,000 20,000 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

In addition to providing greater speeds and bandwidth, DDR2 has other advantages. It uses lower voltage than conventional DDR (1.8V versus 2.5V), so power consumption and heat generation are reduced. Because of the greater number of pins required on DDR2 chips, the chips typically use fine-pitch ball grid array (FBGA) packaging rather than the thin small outline package (TSOP) chip packaging used by most DDR and conventional SDRAM chips. FBGA chips are connected to the substrate (meaning the memory module in most cases) via tightly spaced solder balls on the base of the chip is.

DDR2 DIMMs resemble conventional DDR DIMMs but have more pins and slightly different notches to prevent confusion or improper application. For example, the different physical notches prevent you from plugging a DDR2 module into a conventional DDR (or SDR) socket. DDR2 memory module designs incorporate 240 pins, significantly more than conventional DDR or standard SDRAM DIMMs.

JEDEC began working on the DDR2 specification in April 1998, and published the standard in September 2003. DDR2 chip and module production actually began in mid-2003 (mainly samples and prototypes), and the first chipsets, motherboards, and systems supporting DDR2 appeared for Intel processor–based systems in mid-2004. At that time variations of DDR2 such as G-DDR2 (Graphics DDR2) began appearing in graphics cards as well. Mainstream motherboard chipset support for DDR2 on Intel processor–based systems appeared in 2005. Notable for its lack of DDR2 support through 2005 was AMD, whose Athlon 64 and Opteron processor families included integrated DDR memory controllers. AMD processor–based systems first supported DDR2 in mid-2006, with the release of socket AM2 motherboards and processors to match. (AMD's Socket F, also known as 1207 FX, also supports DDR2 memory.)

It is interesting to note that AMD was almost 2 years behind Intel in the transition from DDR to DDR2. This is because AMD included the memory controller in its Athlon 64 and all subsequent processors, rather than incorporating the memory controller in the chipset North Bridge, as with the more traditional Intel designs. Although there are advantages to integrating the memory controller in the CPU, one disadvantage is the inability to quickly adopt new memory architectures, because doing so requires that both the processor and processor socket be redesigned. However, with the release of the Core i7 processors in 2008, Intel also moved the memory controller from the chipset into the processor, thus putting Intel and AMD in the same situation as far as memory architectures are concerned.

DDR3

DDR3 is the latest JEDEC memory standard. It enables higher levels of performance along with lower power consumption and higher reliability than DDR2. JEDEC began working on the DDR3 specification in June of 2002, and the first DDR3 memory modules and supporting chipsets (versions of the Intel 3xx series) were released for Intel-based systems in mid-2007. Due to initial high cost and limited support, DDR3 didn't start to become popular until late 2008 when Intel released the Core i7 processor, which included an integrated tri-channel DDR3 memory controller. In early 2009, popularity increased when AMD released Socket AM3 versions of the Phenom II, the first from AMD to support DDR3. During 2009, with full support from both Intel and AMD, DDR3 finally began to achieve price parity with DDR2, causing DDR3 to begin to eclipse DDR2 in sales.

DDR3 modules use advanced signal designs, including self-driver calibration and data synchronization, along with an optional onboard thermal sensor. DDR3 memory runs on only 1.5V, which is nearly 20% less than the 1.8V used by DDR2 memory. The lower voltage combined with higher efficiency reduces overall power consumption by up to 30% compared to DDR2.

DDR3 is most suited to systems where the processor and/or memory bus runs at 1,333MHz or higher, which is faster than the 1,066MHz maximum supported by DDR2. For higher-speed memory in standard (non-overclocked) systems, DDR3 modules rated PC3-10600 and PC3-12800 allow for throughputs of 10,667MBps and 12,800MBps, respectively. When combined in dual-channel operation, a pair of PC3-12800 modules result in a total throughput of an incredible 25,600MBps. Processors with tri-channel support, such as the Core i7, have memory bandwidths of 32,000MBps and 38,400MBps using DDR3-1333 and DDR3-1600, respectively. Table 6.10 shows the various official JEDEC-approved DDR3 module types and bandwidth specifications.

Table 6.10. JEDEC Standard DDR3 Module (240-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) Tri-Channel Transfer Rate (MBps) PC3-6400 DDR3-800 400 2 800 8 6,400 12,800 19,200 PC3-8500 DDR3-1066 533 2 1066 8 8,533 17,066 25,600 PC3-10600 DDR3-1333 667 2 1333 8 10,667 21,333 32,000 PC3-12800 DDR3-1600 800 2 1600 8 12,800 25,600 38,400 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

The fastest official JEDEC-approved standard is DDR3-1600, which is composed of chips that run at an effective speed of 1,600MHz (really megatransfers per second), resulting in modules designated PC3-12800 and having a bandwidth of 12,800MBps. However, just as with DDR and DDR2, many manufacturers produce nonstandard modules designed for overclocked systems. These are sold as modules with unofficial designations, clock speeds, and performance figures that exceed the standard ratings.

Table 6.11 shows the popular unofficial DDR3 speed ratings I've seen on the market. Note that because the speeds of these modules are beyond the standard default motherboard and chipset speeds, you won't see any advantage to using them unless you are overclocking your system and your motherboard supports the corresponding overclocked processor and memory settings that these modules require. In addition, because these modules use standard-speed chips that are running overclocked, they almost always require custom voltage settings that are higher than the 1.5V used by standard DDR3 memory. For system stability, I generally don't recommend using overclocked (higher voltage) memory, instead preferring to use only that which runs on the DDR3 standard 1.5V.

Table 6.11. Overclocked (non-JEDEC) DDR3 Module (240-pin DIMM) Speeds and Transfer Rates

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) Dual-Channel Transfer Rate (MBps) Tri-Channel Transfer Rate (MBps) PC3-11000 DDR3-1375 688 2 1375 8 11,000 22,000 33,000 PC3-13000 DDR3-1625 813 2 1625 8 13,000 26,000 39,000 PC3-14400 DDR3-1800 900 2 1800 8 14,400 28,800 43,200 PC3-14900 DDR3-1866 933 2 1866 8 14,933 29,866 44,800 PC3-15000 DDR3-1866 933 2 1866 8 14,933 29,866 44,800 PC3-16000 DDR3-2000 1000 2 2000 8 16,000 32,000 48,000 MTps = Megatransfers per second MBps = Megabytes per second DIMM = Dual inline memory module DDR = Double data rate

The 240-pin DDR3 modules are similar in pin count, size, and shape to the DDR2 modules; however, the DDR3 modules are incompatible with the DDR2 circuits and are designed with different keying to make them physically noninterchangeable.

RDRAM

Rambus DRAM (RDRAM) was a proprietary (non-JEDEC) memory technology found mainly in certain Intel-based Pentium III and 4 systems from 2000 through 2002. Intel had signed a contract with Rambus in 1996 ensuring it would both adopt and support RDRAM memory into 2001. Believing that any memory it endorsed would automatically become the most popular in the industry, Intel also invested heavily in Rambus at the time. Because RDRAM was a proprietary standard owned by Rambus, using or producing it would require licensing from Rambus, something that was not very popular with other memory and chipset manufacturers. Still, the technology was licensed and Intel originally promised that supporting chipsets and motherboards would be available in 1998.

Unfortunately there were problems in getting the supporting chipsets to market, with delays of many months resulting in memory manufacturers stockpiling RDRAM chips with no systems to support them, while conventional SDRAM and DDR meanwhile came into short supply. The delays resulted in an industrywide debacle that caused Intel to rethink and eventually abandon its investment in the technology. After 2001, Intel continued to support RDRAM in existing systems; however, new chipsets and motherboards rapidly shifted to DDR SDRAM. AMD wisely never invested in the RDRAM technology, and as a result no AMD-based systems were ever designed to use RDRAM.

Without Intel's commitment to future chipset development and support, very few RDRAM-based systems were sold after 2002. Due to the lack of industry support from chipset and motherboard manufacturers, RDRAM was only used in PCs for a short time, and will most likely not play a big part in any future PCs.

With RDRAM, Rambus developed what is essentially a chip-to-chip memory bus, with specialized devices that communicate at very high rates of speed. What might be interesting to some is that this technology was first developed for game systems and first made popular by the Nintendo 64 game system, and it subsequently was used in the Sony Playstation 2.

Conventional memory systems that use SDRAM are known as wide-channel systems. They have memory channels as wide as the processor's data or memory bus, which for the Pentium and up is 64 bits, or even wider in dual-channel or tri-channel modes. The dual inline memory module (DIMM) is a 64-bit wide device, meaning data can be transferred to it 64 bits (or 8 bytes) at a time.

RDRAM modules, on the other hand, are narrow-channel devices. They transfer data only 16 bits (2 bytes) at a time (plus 2 optional parity bits), but at faster speeds. This was a shift away from a more parallel to a more serial design for memory and is similar to what has been happening with other evolving buses in the PC.

Each individual chip is serially connected to the next on a package called a Rambus inline memory module (RIMM), which looks similar to a DIMM module but which is not interchangeable. All memory transfers are done between the memory controller and a single device, not between devices. A single Rambus channel typically has three RIMM sockets and can support up to 32 individual RDRAM devices (the RDRAM chips) and more if buffers are used. However, most motherboards implement only two modules per channel (four sockets in a dual-channel design) to avoid problems with signal noise.

The RDRAM memory bus is a continuous path through each device and module on the bus, with each module having input and output pins on opposite ends. Therefore, any RIMM sockets not containing a RIMM must then be filled with a continuity module to ensure that the path is completed. The signals that reach the end of the bus are terminated on the motherboard.

The 16-bit single-channel RIMMs originally ran at 800MHz, so the overall throughput is 800x2, or 1.6GB per second for a single channel—the same as PC1600 DDR SDRAM. Pentium 4 systems typically used two banks simultaneously, creating a dual-channel design capable of 3.2GBps, which matched the bus speed of the original Pentium 4 processors. The RDRAM design features less latency between transfers because they all run synchronously in a looped system and in only one direction.

Newer RIMM versions ran at 1,066MHz in addition to the original 800MHz rate, but very few chipsets or motherboards were released to support the higher speed.

Each RDRAM chip on a RIMM1600 essentially operates as a standalone device sitting on the 16-bit data channel. Internally, each RDRAM chip has a core that operates on a 128-bit wide bus split into eight 16-bit banks running at 100MHz. In other words, every 10ns (100MHz), each RDRAM chip can transfer 16 bytes to and from the core. This internally wide yet externally narrow high-speed interface is the key to RDRAM.

Other improvements to the design include separating control and data signals on the bus. Independent control and address buses are split into two groups of pins for row and column commands, while data is transferred across the 2-byte wide data bus. The actual memory bus clock runs at 400MHz; however, data is transferred on both the falling and rising edges of the clock signal, or twice per clock pulse. The falling edge is called an even cycle, and the rising edge is called an odd cycle. Complete memory bus synchronization is achieved by sending packets of data beginning on an even cycle interval. The overall wait before a memory transfer can begin (latency) is only one cycle, or 2.5ns maximum.

Figure 6.2 (shown earlier) depicts the relationship between clock and data cycles; you can see the DDR clock and data cycles used by RDRAM and DDR SDRAM. An RDRAM data packet always begins on an even (falling) transition for synchronization purposes. The architecture also supports multiple, simultaneous interleaved transactions in multiple separate time domains. Therefore, before a transfer has even completed, another can begin.

Another important feature of RDRAM is that it is designed for low power consumption. The RIMMs themselves as well as the RDRAM devices run on only 2.5 volts and use low-voltage signal swings from 1.0V to 1.8V, a swing of only 0.8V total. RDRAMs also have four power-down modes and can automatically transition into standby mode at the end of a transaction, which offers further power savings.

A RIMM is similar in size and physical form to a DIMM, but they are not interchangeable. RIMMs are available in module sizes up to 1GB or more and can be added to a system one at a time because each individual RIMM technically represents multiple banks to a system. Note, however, that they have to be added in pairs if your motherboard implements dual-channel RDRAM and you are using 16-bit wide RIMMs.

RIMMs are available in four primary speed grades and usually run in a dual-channel environment, so they have to be installed in pairs, with each one of the pairs in a different set of sockets. Each set of RIMM sockets on such boards is a channel. The 32-bit version incorporates multiple channels within a single device and, as such, is designed to be installed individually, eliminating the requirement for matched pairs. Table 6.12 compares the various types of RDRAM modules. Note that the once-common names for RIMM modules, such as PC800, have been replaced by names that reflect the actual bandwidth of the modules to avoid confusion with DDR memory.

Table 6.12. RDRAM Module Types and Bandwidth

 Module Standard Chip Type Clock Speed (MHz) Cycles per Clock Bus Speed (MTps) Bus Width (Bytes) Transfer Rate (MBps) RIMM1200 PC600 300 2 600 2 1,200 RIMM1400 PC700 350 2 700 2 1,400 RIMM1600 PC800 400 2 800 2 1,600 RIMM2100 PC1066 533 2 1,066 2 2,133 MTps = Megatransfers per second MBps = Megabytes per second RIMM = Rambus inline memory module

When Intel initially threw its weight behind the Rambus memory, it seemed destined to be a sure thing for success. Unfortunately, technical delays in the chipsets caused the supporting motherboards to be significantly delayed, and with few systems to support the RIMMs, most memory manufacturers went back to making SDRAM or shifted to DDR SDRAM instead. This caused the remaining available RIMMs being manufactured to be originally priced three or more times that of comparatively sized DIMMs.

With support for RDRAM memory essentially gone by 2003, RDRAM quickly disappeared from the PC marketplace. Because RDRAM is in such limited supply, if you have existing systems with RDRAM memory, it is generally not cost effective to upgrade them by adding more memory.

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