Signal and Power Integrity: Time and Frequency Domains
- 2.1 The Time Domain
- 2.2 Sine Waves in the Frequency Domain
- 2.3 Shorter Time to a Solution in the Frequency Domain
- 2.4 Sine Wave Features
- 2.5 The Fourier Transform
- 2.6 The Spectrum of a Repetitive Signal
- 2.7 The Spectrum of an Ideal Square Wave
- 2.8 From the Frequency Domain to the Time Domain
- 2.9 Effect of Bandwidth on Rise Time
- 2.10 Bandwidth and Rise Time
- 2.11 What Does Significant Mean?
- 2.12 Bandwidth of Real Signals
- 2.13 Bandwidth and Clock Frequency
- 2.14 Bandwidth of a Measurement
- 2.15 Bandwidth of a Model
- 2.16 Bandwidth of an Interconnect
- 2.17 The Bottom Line
We will find that there are multiple ways of looking at a signal, each providing a different perspective. The quickest path to the answer may not be the most obvious path. The different perspectives we will use to look at signals are called domains. In particular we'll use the time domain and the frequency domain.
We will find that while we may generally be more familiar with the time domain, the frequency domain can provide valuable insight to understand and master many signal-integrity effects such as impedance, lossy lines, the power-distribution network, measurements, and models.
After introducing the two domains, we will look at how to translate between the two for some special cases. We will apply what we learn to relate two important quantities: rise time and bandwidth. The first is a time-domain term and the second a frequency-domain term. However, as we will see, they are intimately related.
Finally, we'll apply this concept of bandwidth to interconnects, models, and measurements.
2.1 The Time Domain
We use the term a lot—the time domain. But what do we really mean? What is the time domain? What are the features that are special about the time domain that make it useful? These are surprisingly difficult questions to answer because they seem so obvious and we rarely think about what we really mean by the time domain.
We take it for granted because from the moment we are born, our experiences are developed and calibrated in the time domain. We are used to seeing events happen with a time stamp and ordered sequentially.
The time domain is the world of our experiences and is the domain in which high-speed digital products perform. When evaluating the behavior of a digital product, we typically do the analysis in the time domain because that's where performance is ultimately measured.
For example, two important properties of a clock waveform are clock period and rise time. Figure 2-1 illustrates these features.
Figure 2-1 Typical clock waveform showing the clock period and the 10–90 rise time for a 1-GHz clock. The fall time is typically slightly shorter than the rise time and sometimes creates more noise.
The clock period is the time interval to repeat one clock cycle, usually measured in nanoseconds (nsec). The clock frequency, Fclock, or how many cycles per second the clock goes through, is the inverse of the clock period, Tclock.
- Fclock = the clock frequency, in GHz
- Tclock = the clock period, in nsec
For example, a clock with a period of 10 nsec will have a clock frequency of 1/10 nsec = 0.1 GHz or 100 MHz.
The rise time is related to how long it takes for the signal to transition from a low value to a high value. There are two popular definitions of rise time. The 10–90 rise time is how long it takes for the signal to transition from 10% of its final value to 90% of its final value. This is usually the default meaning of rise time. It can be read directly off the time domain plot of a waveform.
The second definition is the 20–80 rise time. This is the time it takes for the signal to transition from 20% of its final value to 80% of its final value. Of course, for the same waveform the 20–80 rise time is shorter than the 10–90 rise time. Some IBIS models of real devices use the 20–80 definition of rise time. This makes it confusing. To remove ambiguity, it's often good practice referring explicitly to the 10–90 rise time or the 20–80 rise time.
There is a corresponding value for the fall time of a time-domain waveform. Depending on the logic family, the fall time is usually slightly shorter than the rise time. This is due to the design of typical CMOS output drivers. In a typical output driver, a p and an n transistor are in series between the VCC (+) and the VSS (-) power rails. The output is connected to the center, between them. Only one transistor is on at any one time, depending on whether the output is a low or a high.
When the driver switches from a low to a high (i.e., rising edge), the n transistor turns off and the p transistor turns on. The rise time is related to how fast the p transistor can turn on. When switching from the high to the low state (i.e., a falling edge), the p transistor turns off and the n transistor turns on. In general, for the same feature-size transistor, an n transistor can turn on faster than a p transistor. This means switching from high to low, the falling edge will be shorter than the rising edge. In general, signal-integrity problems are more likely to occur when switching from a high to low transition than from a low to high transition. By making the n channel transistor larger than the p channel, the rising and falling edges can be closely matched.
Having established an awareness of the time domain as a distinct way of looking at events, we can turn our attention to one of a number of alternative ways of analyzing the world—the frequency domain.