1.5 IP-Based Design
In this section, we will look at how intellectual property (IP) is used in chip design. All designers will either design IP for others or use IP in their own designs. IP-based design has different aspects, depending on the role of the designer and whether IP is being produced or used. We will start with the motivation for IP-based design, then look at some different types of IP, and then consider the IP-based design process.
1.5.1 Why IP?
Intellectual property is a dominant mode of chip design today simply because of the scale of chips that we can produce. Even modest chips contain millions of transistors and we can now design two billion transistor chips [Fil08]. We passed the point long ago when even a large team can design an entire chip from scratch.
An early form of IP was the standard cell, which dates back to the early 1970s. Standard cells are designed to abut together in a fixed-height row of cells and used by a placement-and-routing program. Standard cell design was created to automate the design of application-specific integrated circuits (ASICs) that were destined for low-volume manufacturing. In such cases, the cost of design exceeded the cost of manufacturing, so a design technique that traded some area for lower design costs was acceptable. Standard cells are still used even in large custom designs for subsystems, like control, where human designers have a harder time finding optimizations.
Today, IP components include the entire range of modules, as we will see in the next section, ranging from standard cells through I/O devices and CPUs. Chip designers need complex IP components because modern levels of integration allow chips to be complete systems, not just components of systems. When designing a system-on-chip, much of the added value comes from the architect’s ability to identify the right combination of components to put on the chip. Many of those components are standardized—either they are based on open standards or they are licensed from IP providers who own a standard (such as an instruction set). In some cases, the chip designers may not have the ability to design an equivalent for the IP component themselves without violating patents or other legal problems. One generation’s chip often becomes the next technology generation’s IP component as more and more elements are integrated onto a single chip. IP-based design is crucial even in the microprocessor world, where a chip consists entirely of one or more CPUs and cache. Several different versions of a processor family are needed to fill the product space; designing the processor as reusable IP makes much more sense than starting from scratch each time. And as multicore processors come to dominate the microprocessor world, processors must be replicated on the die.
1.5.2 Types of IP
Intellectual property as components
A system-on-chip is not useful unless it can be designed in a reasonable amount of time. If all the subsystems of an SoC had to be designed by hand, most SoCs would not be ready in time to make use of the manufacturing process for which they were designed. SoC design teams often make use of IP blocks in order to improve their productivity. An IP block is a pre-designed component that can be used in a larger design. There are two major types of IP:
- Hard IP comes as a pre-designed layout. Because a full layout is available, the block’s size, performance, and power consumption can be accurately measured.
- Soft IP comes as a synthesizable module in a hardware description language such as Verilog or VHDL. Soft IP can be more easily targeted to new technologies but it is harder to characterize and may not be as small or as fast as hard IP.
The simplest and earliest example of a hard IP block is the standard cell, which is a gate-level IP component. Hard IP components are designed for a particular manufacturing process and its design rules. If the hard IP block is to be used in a different process, it must be redesigned.
Hard IP blocks must conform to a variety of standards relating to the physical and electrical characteristics of the process and of the other blocks designed in that process. A given process may dictate that certain types of signals appear on certain layers; an IP library may further dictate that certain types of signals appear at specific positions on the block. The block must also be defined to an electrical standard—it must be able to drive a certain load at some specified delay, for example.
Most important hard IP blocks that are sold by vendors are qualified for a given process. The qualification procedure consists of fabricating the IP block in the process and then testing the resulting chips. Qualification assures the customer that the block works functionally, that it meets its stated performance goals, etc.
Soft IP is designed to be implemented using logic synthesis and place-and-route tools. As such, it is more easily targeted to a new manufacturing process, perhaps at some cost in performance, power, and area. A surprising number of large blocks, including CPUs, are delivered only as soft IP. The design time savings of soft IP often outweigh the cost and performance savings, even for such large IP blocks.
Although details of the physical interface to the IP block can be handled by the design flow, a soft IP block must still be designed to implement an interface that allows it to be connected to other blocks on the chip. In some cases, a block’s interface may need to be changed—for example, if a different type of bus is used to connect the blocks. The logic used to adapt the interface is often called a wrapper.
Because a soft IP block is delivered in synthesizable form, it is more easily stolen than a hard IP block. Soft IP vendors may tag their blocks to more easily trace their source.
1.5.3 IP Across the Design Hierarchy
The standard cell is one of the earliest examples of IP. A family of standard cells is designed together both to provide a useful set of logical functions and to have compatible layouts. The cells can be placed side-by-side in any order. The signals between the cells are then wired using computer-aided design tools. Standard cells are still widely used today.
Larger modules, like those used in register-transfer logic design, are also good candidates for encapsulation as IP. Many of these components are bit-oriented, which means that one bit of the function can be designed and then be replicated to create an n-bit component. Adders, ALUs, and even complete datapaths make good IP components.
Memory is an important category of IP. Memory circuits are analog designs that must be carefully crafted. The memory cells themselves are necessarily delivered as hard IP for all but the simplest of memories. However, much of the complexity of memory IP comes from their use in systems. Memories may be needed in many different sizes and aspect ratios; generators are often used to generate a specific memory configuration. Memories also require a great deal of peripheral circuitry to be useful in systems. Memory controllers, bus interfaces, and other logic is also critical to the system interface to the memory core. Some of this associated logic may be delivered as soft IP.
One critical type of IP for SoC design is the embedded CPU. An embedded processor can be programmed to perform certain functions on the chip, much as an embedded processor is used in a board design. Embedded CPUs have been used on chips for many years: early embedded processors were mostly 8-bit CPUs used for basic sequencing; today, powerful 32-bit CPUs can be embedded on a system-on-chip. The fact that not just the CPU but also its cache, main memory, and I/O devices can be integrated on the same chip make embedded processors especially attractive.
Embedded CPUs are increasingly popular on SoCs for several reasons. First, many sophisticated applications are best implemented in software. Multimedia applications like MP3 audio and MPEG video are examples of functions that are difficult to implement without some amount of embedded software. Second, many complex systems must run embedded software in order to implement their applications. For example, digital audio systems must run digital rights management software that is available only in binary form. Many systems-on-chips also use Linux, Windows CE, or some other OS to provide file management and networking. Third, embedded CPUs help decrease design time. Because the embedded processor is a relatively well-understood component, the design of the software can be somewhat decoupled from the hardware design.
Some CPUs are delivered as hard IP. However, the majority of CPUs are delivered as soft IP. The CPU’s functionality may be fixed. A configurable CPU is one whose features are selected by the designer; a CPU is then created to match the specs, typically using a generator. A configurable CPU may provide options for custom instructions, registers, bus interfaces, or almost any aspect of the CPU.
Buses (and other forms of system interconnect) are essential for CPU-oriented designs. The bus connects the processing elements, memories, and devices. The bus interface is a natural boundary for the interfaces to be implemented by IP components.
Because the bus connects to a large majority of the IP components on the SoC, many IP providers must be able to use the bus standard. One example of an open bus standard is the AMBA protocol (http://www.amba.com).
SoCs include many I/O devices. Because I/O devices are themselves usually defined by standards, they are natural candidates for embodiment as IP. I/O devices are often delivered as soft IP because they must be ported to many technologies and because they often don’t require the fastest implementation.
1.5.4 The IP Life Cycle
IP differs from custom chip design in that it is designed well before it is used. The life cycle of IP components may stretch over years from the time the IP modules are first created, through several generations of technology, to their final retirement.
IP life cycle
Figure 1-8 shows the IP life cycle in two stages: IP creation and IP use. Creation starts with a specification and goes through all the normal design processes, using hardware description languages and, in the case of hard IP, layout design tools. However, the IP modules go through more extensive testing since they will be used many times. IP creation results in the IP modules themselves, plus documentation and database descriptions. The database information is used by design tools for layout, performance analysis, etc. All this information feeds into standard chip design processes.
Figure 1-8 The IP life cycle.
1.5.5 Creating IP
When we create intellectual property, we must first specify the module we want to design. Specification is a challenge because it must be done in cooperation with the potential users of the IP. If we do not start with a specification that is likely to attract enough users, then there is no point in designing the IP block.
The specification must cover many aspects of the final design:
- whether the module will be hard or soft IP;
- performance, not just average case but at various combinations of process parameters;
- power consumption;
- what types of process features are required to support the module.
Once we have decided what to design, we need to follow design methodologies that ensure we will end up with an implementation that meets our specification. Our design methodology must also support the extra work that we have to do in order to reuse our IP modules. In general, we need to test modules more thoroughly at each stage in the design process and run a rigorous set of tests. The basic form of the tests will be determined by the ways in which the IP module will be used.
Documentation is important in any design but critical to a design that will be widely disseminated. The IP block must be documented in sufficient detail that others can use it in a variety of circumstances; that documentation must go beyond functionality to circuit, etc. The nature of the documentation required for an IP module may be dictated by the organization that will distribute the IP.
In order to be useful, the module must be entered into databases used by various tools: place-and-route, timing analysis, etc. A great deal of information is required to describe the module for all these tools. Specialized methodologies are generally used to generate the required database descriptions from the module implementations.
An IP module must be shown to provide a given performance and power level not just in the average case, but in a variety of conditions: variations in fabrication process parameters, temperature variations, etc. The process of determining the operational characteristics of a module over a range of parameters is known as characterization. Characterization requires extensive simulation at the circuit level and other levels. Each simulation is at one set of parameters; these parameter sets must be chosen to adequately cover the space of variations that must be verified.
A step beyond characterization is qualification, in which the module is fabricated and physically tested. This qualification exercise is used to show that the module works in one process—if you want to use the module in another process, then you must fabricate it again on the new process.
1.5.6 Using IP
Sources of IP
IP blocks come from a variety of sources. A number of vendors sell IP blocks. Some IP vendors are large companies; in other cases, individuals may sell IP. The OpenCores Web site (http://www.opencores.org) provides a number of IP blocks that are available under open source licensing.
Identifying candidate IP modules
In order to find IP modules that will be useful in your design, you should look at all the elements of the specification of the IP blocks. Functionality is certainly an easy filter to rule out many modules, but you also have to check the power/performance trade-offs of the cells, what processes they are designed for, etc.
IP modules can come from a variety of sources: foundries, independent IP vendors, or shareware. A foundry often provides basic IP—standard cells, I/O pads, etc.—that are optimized for their process. Some foundries may require payment for their IP, while others may not. (For example, a fab line may provide many cells for their process in order to attract customers.) Independent of whether the modules are paid for, the vendor may require the user to agree to certain terms of usage, such as whether they will reveal the design to others. Acquiring IP takes time, so the IP acquisition process should be factored into the total chip design time.