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Itanium (P7/Merced) Seventh-Generation Processors

What is coming after the Pentium III? The next-generation processor was code-named either P7 or Merced and will be called Itanium.

Intel has indicated that the new 64-bit Itanium processor will be available in late 2000. The Itanium processor will be the first processor in Intel's IA-64 (Intel Architecture 64-bit) product family and will incorporate innovative performance-enhancing architecture techniques, such as prediction and speculation.


The most current generation of processor is the P6, which was first seen in the Pentium Pro introduced in November of 1995 and most recently found in the latest Pentium II processors. Obviously, then, the next generation processor from Intel will be called the Itanium.

Intel's IA-64 product family is expected to expand the capabilities of the Intel architecture to address the high-performance server and workstation market segments. A variety of industry players—among them leading workstation and server-system manufacturers, leading operating system vendors, and dozens of independent software vendors—have already publicly committed their support for the Itanium processor and the IA-64 product family.

As with previous new processor introductions, the P7 will not replace the P6 or P5, at least not at first. It will feature an all new design that will be initially expensive and found only in the highest end systems such as file servers or workstations. Intel expects the Itanium will become the mainstream processor by the year 2004 and that the P6 will likely be found in low-end systems only. Intel is already developing an even more advanced P7 processor, due to ship in 2001, which will be significantly faster than Itanium.

Intel and Hewlett-Packard began jointly working on the P7 processor in 1994. It was then that they began a collaboration on what will eventually become Intel's next-generation CPU. Although we don't know exactly what the new CPU will be like, Intel has begun slowly releasing information about the new processor to prepare the industry for its eventual release. In October of 1997, more than three years after they first disclosed their plan to work together on a new microprocessor architecture, Intel and HP officially announced some of the new processor's technical details.

The first chip to implement the P7 architecture won't ship until late 2000.

Itanium will be the first microprocessor that will be based on the 64-bit, next-generation Intel architecture-64 (IA-64) specification. IA-64 is a completely different processor design, which will use Very Long Instruction Words (VLIW), instruction prediction, branch elimination, speculative loading, and other advanced processes for enhancing parallelism from program code. The new chip will feature elements of both CISC and RISC design.

There is also a new architecture Intel calls Explicitly Parallel Instruction Computing (EPIC), which will let the processor execute parallel instructions—several instructions at the same time. In the Itanium, three instructions will be encoded in one 128-bit word, so that each instruction has a few more bits than today's 32-bit instructions. The extra bits let the chip address more registers and tell the processor which instructions to execute in parallel. This approach simplifies the design of processors with many parallel-execution units and should let them run at higher clock rates. In other words, besides being capable of executing several instructions in parallel within the chip, the Itanium will have the capability to be linked to other Itanium chips in a parallel processing environment.

Besides having new features and running a completely new 64-bit instruction set, Intel and HP promise full backward compatibility between the Itanium, the current 32-bit Intel x86 software, and even HP's own PA-RISC software. The P7 will incorporate three different kinds of processors in one and therefore be capable of running advanced IA-64 parallel processing software and IA-32 Windows and HP-RISC UNIX programs at the same time. In this way, Itanium will support 64-bit instructions while retaining compatibility with today's 32-bit applications. This backward compatibility will be a powerful selling point.

To use the IA-64 instructions, programs will have to be recompiled for the new instruction set. This is similar to what happened in 1985, when Intel introduced the 80386, the first 32-bit PC processor. The 386 was to give IBM and Microsoft a platform for an advanced 32-bit operating system that tapped this new power. To ensure immediate acceptance, the 386 and future 32-bit processors still ran 16-bit code. To take advantage of the 32-bit capability first found in the 386, new software would have to be written. Unfortunately, software evolves much more slowly than hardware. It took Microsoft a full 10 years after the 386 debuted to release Windows 95, the first mainstream 32-bit operating system for Intel processors.

Intel claims that won't happen with the P7. Despite that, it will likely take several years before the software market shifts to 64-bit operating systems and software. The installed base of 32-bit processors is simply too great, and the backward compatible 32-bit mode of the P7 will allow it to run 32-bit software very well, because it will be done in the hardware rather than through software emulation.

Itanium will use 0.18 micron technology for the initial Merced chips. This will allow Itanium to pack many more transistors in the same space. Early predictions have the Itanium sporting 100 million transistors!

Intel's initial goal with IA-64 is to dominate the workstation and server markets, competing with chips such as the Digital Alpha, Sun Sparc, and Motorola PowerPC. Microsoft will provide a version of Windows NT that runs on the P7, and Sun plans to provide a version of Solaris, its UNIX operating-system software, to support Itanium as well. NCR has already announced that it will build Itanium-powered systems that use Solaris.

Itanium will be available in a new package called the Pin Array Cartridge (PAC). This cartridge will include cache and will plug into a socket on the motherboard and not a slot. The package is about the size of a standard index card, weighs about 6oz (170g) and has an alloy metal on its base to dissipate the heat. (See Figure 3.58.) Itanium has clips on its sides, allowing four to be hung from a motherboard, both below and above.

Figure 3.58 Itanium processor.

Itanium will have three levels of cache. The L1 cache will be closely tied to the execution unit. It will be backed by on-die L2 cache. Finally the multimegabyte L3 cache will be housed in separate chips contained within the cartridge.

Itanium will be followed in late 2001 by a second IA-64 processor code-named McKinley. McKinley will have larger on-die L2 cache and target clock speeds of more than 1.5GHz, offering more than twice the performance of Itanium, according to Intel reps. Following McKinley will be Madison, based on 0.13 micron technology. Both Itanium and McKinley are based on 0.18 micron technology.

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