# Basic Concepts for Semiconductor Power Delivery

• Print
This chapter is from the book

## 1.8 Signal Lines Referenced to Planes

In high-frequency packages and PCBs, the signal lines are often routed over or between planes. The planes provide shielding for the signal lines by minimizing coupling between the signal lines routed on the same layer or on different layers. In addition, the planes perform a very important function by carrying return current of the signal lines. Any discontinuities in the return current of the signal lines can cause SSN. Hence, to model SSN arising from the switching of I/O drivers, a good knowledge of the return path discontinuities is necessary. Placement of the capacitors at the return path discontinuities reduces SSN. In this section, the transmission line equations are derived along with a discussion, using two examples, on the importance of return currents.

### 1.8.1 Signal Lines as Transmission Lines

Signals cannot propagate faster than the speed of light. The velocity of 3 x 108 m/s in air is roughly equivalent to a time delay of 1 ns per foot of travel. In FR-4 (a common dielectric material used to fabricate PCB), a signal takes 1.66 ns to travel a distance of 10 inches. This delay can be an entire clock period behind and hence can slow down the system. Analyzing such signal lines using Kirchhoff's voltage and current laws neglect this time delay and can provide erroneous results. Early ICs involved transistor–transistor logic (TTL) devices with internal delays of 15 ns or more, limiting the clock rates to lower levels and making the transit time of the signals negligible in comparison. Modern devices have improved to the point that signal delays are the limiting factor in digital circuit design. Transmission line theory in which signal lines are analyzed as distributed circuits explicitly includes this time delay and therefore is applicable to these situations.

To better explain transmission line theory, consider a coaxial cable, as shown in 1-45(a), consisting of two conductors separated by a dielectric material. When current flows on the coaxial cable, there is a physical movement of charge carriers (electrons) down one conductor and back on the other. If there is a current flow into the inner conductor, then the return current flows in the opposite direction on the outer conductor. Because of this movement, the charge has some momentum, and the current therefore wants to keep moving once it has started. This effect is equivalent to some series inductance in the cable.

There is also some series resistance, since the metal is not a "perfect" conductor of electricity, and some of the electrical energy is therefore converted to heat as the current flows. At the same time, equal and opposite charge is stored instantaneously on the two conductors, giving rise to some shunt capacitance. If the material separating the conductors is not a perfect insulator, there will also be some leakage current from one conductor to another, which is the shunt conductance .

Although coaxial cables are excellent transmission lines, since the return current is always in close proximity to the forward current, it is difficult to use them in ICs, packages, and boards because of their three-dimensional structure. Hence, planar structures such as microstrip and striplines are used where the reference conductor is in the form of planes. The planes carry the return current, so it is important to locate the reference plane in close proximity to the signal conductor. An example of a microstrip line is shown in Figure 1-45(b).

Since the cross section of a transmission line is uniform and its length is much larger than its cross section, it can be described using the pul resistance (R), inductance (L), conductance (G), and capacitance (C) parameters. A small section of a transmission line can be represented using the equivalent circuit shown in Figure 1-46, where the pul parameters R, L, G, and C are each multiplied by the length Dz. The pul inductance L is the loop inductance between the signal line and the reference plane, where the forward current on the signal line returns in the opposite direction through the reference plane. The pul resistance R in Figure 1-46 is the sum total of the signal and reference plane resistance. The pul capacitance C and conductance G are measured between the singal and reference conductors.

Applying Kirchoff's voltage and current laws to the circuit in Figure 1-46, the following two equations can be obtained:

Equation 1.49

Under the limit Dz → 0, the transmission line equations can be written in the form

Equation 1.50

Equation (1.50) can be extended to multiple coupled lines and form the multiconductor transmission line equations.

### 1.8.2 Relationship between Transmission-Line Parameters and SSN

Two important parameters that describe a transmission line are its characteristic impedance (Z0) and delay (T). For a lossless line (R = 0 and G = 0), these parameters are given by

Equation 1.51

where l is the length of the transmission line. The SSN has an inverse relationship with Z 0, as described by equation (1.10). A transmission line with high characteristic impedance will always require less current to charge the line and hence a smaller dI/dt, which translates into lower SSN. A transmission line with low Z0 is capacitive and hence requires a larger current, resulting in larger SSN. Figure 1-47(a) shows the variation of the SSN as a function of tr/(L/Z0) based on equation (1.9). From the figure, for tr = 0.1 ns and L = 1 nH, a 50-W line will result in an SSN voltage of 0.2 V as compared to 0.1 V for a 100-W line.

Noise on the power supply always results in an extra delay for the signal to rise to the required voltage in addition to the delay of the transmission line, as described by equations (1.12) and (1.13). Therefore, timing errors can occur when the SSN is large, which in turn is related to the Z0 of the transmission line. Figure 1-47(b) shows the variation of the 50% delay as a function of tr/(L/Z0) for a bus, based on equation (1.12) when tr is greater than L/Z0. From the figure, for tr = 0.1 ns and L = 1 nH, a 10 bit wide bus with impedance of 50 W will result in a delay of 0.191 ns as compared to 0.1235 ns for a bus with impedance of 100 W. Hence, choosing the right characteristic impedance for the signal lines becomes very important for minimizing SSN and timing error.

### 1.8.3 Relationship between SSN and Return Path Discontinuities

To illustrate the relationship between SSN and return path discontinuities for signal lines, two examples are discussed here. Figure 1-48(a) consists of a microstrip line over a voltage and ground plane. The signal line is referenced to the voltage plane, and the plane is continuous. A 1-A current source is applied between the input end of the signal line and the voltage plane that creates a forward current on the signal line, as shown in the figure. The return current flows on the voltage plane just beneath the signal line (at high frequencies), so the current loop is completed between the signal line and the voltage plane. This return current does not create any voltage disturbance between the voltage and ground plane, as illustrated in Figure 1-49(a), where a two-dimensional plot of the voltage fluctuation between the two planes is shown as a function of position, indicating that there is no change in the voltage across the planes. Any voltage measured between the two planes, as in Figure 1-48(a), will show no coupling between the signal line and voltage/ground plane. Figure 1-48 (a) Microstrip line above voltage and ground plane. (b) Microstrip line above slot in voltage plane. Figure 1-49 (a) Voltage disturbance on power/ground plane for ideal microstrip. (b) Voltage disturbance on power/ground plane for microstrip above slot.

Now consider a slot on the voltage plane beneath the signal line, as shown in Figure 1-48(b). With a 1-A current source excitation between the signal line and voltage plane, the forward current on the signal line causes a return current on the voltage plane. At the slot, the return current flows on the ground plane (due to the absence of metal on the voltage plane). Therefore, the current loop is completed by the vertical currents shown in Figure 1-48(b) (also called displacement currents) and is a return path discontinuity that excites the voltage/ground plane and causes a voltage disturbance. The voltage disturbance is shown in Figure 1-49(b) as a two-dimensional plot for a 250 mm by 250 mm plane with a 50-mm slot at the center. The excitation of the voltage/ground plane causes the f01 mode based on equation (1.29) at a frequency of about 750 MHz for a dielectric material with relative permittivity of 4.0 between the planes. Any voltage measured between the two planes, as in Figure 1-48(b), will now show singificant coupling between the signal line and voltage/ground plane. The return path discontinuity effect is discussed in more detail in Chapter 3.

A capacitor with a resonant frequency of 750 MHz placed between the voltage and ground planes near the slot will provide a low impedance path for the current to return on the planes and therefore will reduce the voltage disturbance on the planes.

In summary, SSN caused by the switching of signal lines in the package and board is caused by the return path discontinuities. For high-frequency system applications, the referencing of signal lines to planes is very important. The return path discontinuity for signal lines can be evaluated by following the return current path on the planes. Any discontinuity will manifest itself as voltage fluctuations between voltage and ground. It is important to note that the connection of the drivers and terminations to the signal lines can alter the power supply noise, since the current loop can change at the input and output, as described in Chapter 3.