# Basic Concepts for Semiconductor Power Delivery

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## 1.6 Chip-Package Antiresonance: An Example

The interaction between the chip and package can cause a large antiresonance in the impedance profile of a chip, as described briefly earlier. Large voltage fluctuations can occur if the operating frequency of the chip coincides with the chip-package antiresonance frequency. This effect is best illustrated through an example. Consider a multilayered board of dimension 30 cm by 25 cm, as shown in Figure 1-37(a). The board contains a VRM at one corner with a number of decoupling capacitors. The package assembled on the board is a laminate package with cross section, as shown in Figure 1-37(b), and is 40 mm by 40 mm in size. The package contains an 800-mm core with four sequential build-up layers on either side of the core. The package is assembled on the board through solder balls. The chip of size 15 mm by 15 mm is mounted on the package through C4 solder bumps.

Consider the core PDN where the VRM supplies current to the core transistors of the IC. The core PDN can be represented using an equivalent circuit, as shown in Figure 1-38, where the 1-V VRM is assumed to be represented as an ideal power supply. The two-port impedance between the VRM and bottom of the package is a 2 x 2 matrix with elements Z11, Z12, and Z22, which represent the self-impedance at the VRM, transfer impedance, and self-impedance at the bottom of the package (assumed as a single node at the center of the package). This 2 x 2 matrix can be represented as a T-network with elements Z11 - Z12, Z12, Z22 - Z12, which are all functions of frequency, as shown in Figure 1-38. This circuit representation is one of many possible ways to represent a two-port network. The impedance Zboard(f) at the bottom of the package can be calculated from Figure 1-38 as

Equation 1.34

The impedance at the bottom of the package looking toward the VRM is plotted in Figure 1-39. The frequency response assumes a certain number of decoupling capacitors mounted on the board at various locations. As expected, the impedance has resonances and antiresonances due to the resonant frequency of the capacitors and becomes inductive beyond 100 MHz. Let's assume for simplicity that the package is represented through an equivalent inductance whose impedance is represented as Zpackage in Figure 1-38. The inductance of such a package can be calculated approximately by separating the package into layers consisting of solder bumps, sequential build-up layers, core, and solder balls, then modeling the inductance of the bumps, vias, and balls. This is a good approximation, since the current flows vertically through such multilayered ball grid array packages. A tool called FastHenry [27], available in the public domain, has been used here to generate Table 1-3. In the table, each power/ground bump/via/ball pair has been modeled as a cylinder to extract the self- and mutual partial inductance. The loop inductance for a pair is then calculated using Lloop = Lself1 + Lself2-2M (since current flows in opposite directions for a power/ground loop). The equivalent inductance for a number of these pairs in parallel is then computed by dividing the loop inductance by the total number of pairs present in the package.

#### Table 1-3. Inductance Contributions in a Multilayered Laminate package

 Physical Dimensions Lself1 Lself2 M Lloop Number of Pairs Equivalent Inductance C4 Solder Bump diameter = 90 mm, pitch = 192 mm 15.67 pH 15.67 pH 4.24 pH 22.87 pH 2000 0.01 pH Vias through Build-up diameter = 50 mm, length = 35 mm (x 8 layers), pitch = 192 mm 4.82 pH (x8) 4.82 pH (x8) 0.64 pH (x8) 8.35 pH (x8) 2000 0.03 pH Vias through Core diameter = 300 mm, length = 800 mm, pitch = 707 mm 246.5 pH 246.5 pH 84.57 pH 323.8 pH 145 2.23 pH Solder Balls diameter = 500 mm, length = 500 mm, pitch = 1000 mm 86.67 pH 86.67 pH 25.17 pH 122.98 pH 112 1.09 pH

As can be seen from Table 1-3, the largest contributors to package inductance are the core and the solder balls. Adding the equivalent loop inductances (in series), the package inductance from the solder ball to the C4 bump can be estimated as 3.37 pH. Since Table 1-3 is an approximate method for calculating the equivalent loop inductance, let's assume that the package inductance is ~4 pH. The impedance of a 4-pH inductor is plotted in Figure 1-39, which is a straight line with positive slope on a log-log graph. The total impedance from the top of the package looking into the VRM can now be calculated from Figure 1-38 as

Equation 1.35

The plot of equation (1.35) is shown in Figure 1-39. At low frequencies (<10 MHz), the impedance is dominated by the board, while above 50 MHz, the inductance of the package dominates and the inductance is primarily due to the package inductance. The chip can be represented as a capacitor. Let's assume that the IC capacitance is 500 nF. The impedance of the chip capacitor is plotted in Figure 1-39. The impedance seen from the IC looking toward the VRM can be calculated from Figure 1-38 as

Equation 1.36

since the impedances are in parallel.

This calculation is plotted in Figure 1-39. As can be seen from the figure, an antiresonance occurs at around 100 MHz with a corresponding large impedance. This large impedance is caused by chip-package antiresonance. From Figure 1-39, the chip-package antiresonance occurs at the frequency where Zchip and Zpackage intersect. Hence, the chip-package antiresonance is caused by the parallel resonance of the chip capacitance and package inductance. The board inductance has little to do with causing the antiresonance.

The importance of the chip, package, and board for managing the PDN impedance is shown qualitatively in Figure 1-40. At frequencies from DC to 10 MHz, the board design becomes very critical for managing the target impedance with no contribution coming from either the IC or package. Between 10 and 100 MHz, the interaction between the package and board becomes important. It can cause a shift in the resonance and increase the overall inductance. From 100 MHz to 1 GHz, the interaction between the chip and package can cause an impedance peak due to the antiresonance between the package inductance and IC capacitance. This is the frequency range at which chip–package co-design becomes critical. Beyond 1 GHz, the PDN impedance is dictated solely by the IC capacitance with neither the package nor the board having any influence.