# Basic Concepts for Semiconductor Power Delivery

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## 1.3 Design of PDNs

Since a computer system supports multiple frequencies, a PDN is best designed in the frequency domain. The response of the PDN to switching circuits can then be viewed in the time domain to evaluate the transient noise voltages generated on the power supply terminals of the IC or between any other nodes in the system. The response of the PDN in the frequency domain enables a designer to understand all the resonances and antiresonances in the system produced by the interaction of inductances and capacitances in the network. An antiresonance, when excited by a source, always generates the maximum noise voltage across the power supply terminals of the IC. Based on the frequency response of the PDN, the designer can evaluate the importance of the antiresonances in the system and decide if the source (switching circuits) will ever excite these antiresonances. Hence, the signature of the source along with the frequency response of the PDN decides the noise voltages on the power supply in the time domain. In this section, the concept of target impedance is introduced. The use of target impedance as a design parameter is discussed by evaluating a simple circuit in the frequency and time domain.

### 1.3.1 Target Impedance

The target impedance is based on Ohm's law, which states that the ratio of voltage to current has to equal the impedance in the network. For a PDN, the voltage is the allowed ripple (Dv) on the power supply. The target impedance ZT (in ohms) of a PDN can then be calculated as [7]

Equation 1.16

where the average current drawn by the switching circuits is assumed to be 50% of the maximum current and Vdd is the power supply voltage. Assuming a voltage of 5 V with a ripple of 5% and a maximum current of 1 A, the target impedance can be calculated as

Equation 1.17

The maximum current drawn by an IC can always be calculated by using the relationship P = VImax, since both power P and voltage V for an IC are known. The target impedance ZT establishes an upper limit for the maximum impedance for the PDN across the power supply terminals of the IC in the frequency domain. An impedance below ZT ensures that any current transients will always generate noise voltages of less than 5% of 5 V. Hence, ZT is a very useful parameter for designing PDNs in which the noise voltages have to be controlled within, say, 5% of the supply voltage.

A plot of ZT versus frequency is shown in Figure 1-12. The frequency axis represents the frequency components associated with the source excitation. According to the figure, if the impedance exceeds the target impedance at any frequency where the current transients can excite the network, then the resulting power supply noise will exceed 5% of 5 V = 250 mV. The figure assumes that the magnitude of the current transients is 50% of the maximum current.

The target impedance calculations for five microprocessors introduced between 1990 and 2002 are shown in Table 1-1. As can be seen, the target impedance has decreased 500-fold over a decade because of the lowering of the supply voltage and increase in power. Since the impedance of the PDN is also given by , where L and C are the inductances and capacitances in the network, a low target impedance always implies large capacitance and low inductance in the network. In Table 1-1, the frequency of the microprocessor has increased from 16 MHz to 1.2 GHz over a decade, which implies that the target impedance has to be maintained at least up to the fundamental frequency of the clock. However, this overly restrictive condition may not be satisfied at all frequencies and can often increase the cost of the system. Hence, care should be taken to correlate the frequency response with the current transients in the system to better understand the frequencies at which the PDN will be excited. The target impedance should be maintained at these excitation frequencies.

#### Table 1-1. Target Impedance Trends

 Year Voltage (Volts) Power dissipated (Watts) Current (Amps) Ztarget (mW) Frequency (MHz) 1990 5.0 5 1 250 16 1993 3.3 10 3 54 66 1996 2.5 30 12 10 200 1999 1.8 90 50 1.8 600 2002 1.2 180 150 0.4 1200 Information from Smith [7].

### 1.3.2 Impedance and Noise Voltage

Consider the circuit shown in Figure 1-13(a). The circuit has a supply voltage of 2.0 V. The 3-mW resistance and 320-pH inductance are the spreading resistance and inductance from the power supply to the capacitor. Spreading resistance and inductance produce resistive and inductive drops when the current travels from the power supply to the capacitors (through the interconnects) for charging them. The capacitor parameters are equivalent series resistance (ESR) = 10 mW, equivalent series inductance (ESL) = 1 nH, and C = 100 mF, resulting in a resonant frequency of 0.5 MHz, which are explained in detail later. The on-chip capacitance is 800 nF in the circuit. The current source is 1 A between the voltage and ground terminals of the IC, and through an AC analysis, the voltage (or impedance in ohms) can be obtained as shown in Figure 1-13(b). In Figure 1-13(a), a 1-A current source is used to represent the current, and hence the voltage across it is the impedance in ohms (Z = V/I). In the frequency response, the resonant frequency of the decoupling capacitor can be seen, and the large impedance at approximately 13 MHz is caused by the antiresonance between the chip capacitance and ESL of the decoupling capacitor, which is explained later. The null in the impedance profile is called a resonance; the peak in the impedance profile is called the antiresonance. For a 2-V supply, 5% tolerance, and a 10-A average current, the target impedance is 10 mW. Therefore, the maximum impedance allowed across the current source (which represents the switching circuit) is 10 mW. Clearly, the target impedance is met up to a frequency of 5 MHz in Figure 1-13(b). In the frequency range from 5 MHz to 100 MHz, the target impedance has been exceeded.

Let's now look at the response of this network to two current signatures. The circuit used to compute the time-domain response is shown in Figure 1-14(a). The switching circuit is represented using a time-dependent resistor, the resistance of which changes from 97 mW to 197 mW, which corresponds to a 10-A change in current in the circuit, assuming only 3 mW of resistive impedance (no inductance) is present in the PDN. The current changes from 20 A (2/100 mW) to 10 A (2/200 mW) in the circuit. The voltage across the time-dependent resistor is shown in Figure 1-14(b) for a current transient with rise time of 10 ns and period of 1 ms. As explained earlier, the transient voltage across the IC power supply contains transients with both positive and negative peaks. The noise voltage settles to within 5% of 2 V after 50 ns following the switching activity. Hence, during a large part of the 1-ms period, the noise is below the 5% tolerance value. The 10-ns rise time has enough frequency components that exceed the target impedance initially, causing the first negative glitch to exceed the 100 mV tolerance value. If this negative glitch is a problem, then the impedance at frequencies corresponding to the rise time must be reduced.

Let's now consider the noise voltage when the current transient has a rise time of 10 ns and period of 80 ns, corresponding to a frequency of about 13 MHz, which coincides with the antiresonant frequency. The noise voltage is shown in Figure 1-14(c), which is 200 mV for the entire period of 1 ms and hence exceeds the noise budget of 100 mV. This example shows the importance of managing the impedance of the PDN in the frequency domain to manage excessive noise caused by the current transients.