Motivations to Develop a Simulation Strategy
Most signal integrity engineers would agree that the primary motivation for simulating chip-to-chip networks is to maximize the probability that those networks will function flawlessly on first power-up. There is another compelling motivation that is easy to overlook under the intense pressure of time-to-market: understanding operating margins. It is tempting to stitch together IO circuit and interconnect models, run the simulations, check the results, and be done with the exercise. This may prove that the network will function under a given set of conditions, but will the network continue to function reliably over the range of manufacturing and operating conditions it will encounter during the useful life of the product? What are the expected primary failure mechanisms, and how do they interact with one another?
These questions lie at the heart of signal integrity engineering, and it may be possible to answer them given unlimited resources and time. Unfortunately, most signal integrity engineers are operating under somewhat different circumstances. A contemporary PC board design may have thousands of nets that belong to two or three dozen different buses. The power spectrum for these nets will likely have significant content above 5 GHz. Supplying power and cooling to high-performance processors and low-performance chips on 20 different power supply voltages can place challenging constraints on layout and routing.
On top of these technical challenges, the customer may require that the product be ready for manufacturing in a time period that severely stresses the ability of the team to carry out the level of analysis required to ensure reliable operation. This is the irony of the business: The relevant physical effects become ever more difficult and expensive to analyze while the market relentlessly exerts downward pressure on cost and schedule. Two freight trains are running full speed toward each other on the same track.
Given these technical and business challenges, is it still possible to achieve the goal of reliable operation of a system filled with dozens of digital IO buses over the lifetime of the product? At times it may appear that the solution to this difficult problem is the empty set. In the heat of battle, the level of complexity can be so overwhelming that it seems impossible to satisfy all the constraints simultaneously. Nevertheless, it is possible to successfully manage the signal integrity of a complex contemporary design if the team develops a comprehensive simulation and measurement strategy that applies the appropriate level of analysis to each net in the system.