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This chapter is from the book

This chapter is from the book

3.3 Simulator Variables

In Chapter 2, we discussed two hierarchies in an e-based environment.

  1. The design hierarchy represented in Verilog or VHDL.

  2. The verification hierarchy represented in e

An example of the two hierarchies is shown in Figure 3-1 below

03fig01.gifFigure 3-1. Verification and Design Hierarchies

Any e structure should be able to access the simulator variables for reading or writing during simulation. The subsections below explain how to read and write simulator variables.

3.3.1 Driving and Sampling DUT Signals

In e, one can access simulator variables by simply providing the hierarchical path to the variable within single quotes (''). The example below shows how to access the design hierarchy shown in Figure 3-1.

<'
struct driver{ //Struct in the e environment
r_value: uint(bits:4); //Define a 4 bit field to read

read_value() is { //Define a method to read simulator
                  //variable
   //Right hand side is the simulator variable
   //operand is a variable in module add in Verilog/VHDL
   //The "/" represents the traversal of hierarchy
   //Left hand side is an e field in struct driver
   r_value = '~/top/processor/FPU/add/operand';
};

write_value() is { //Define a method to write simulator
                  //variable
   //Left hand side is the simulator variable
   //Right hand side can be a constant, an e variable,
   //or a simulator variable.
   '~/top/processor/FPU/add/operand' = 7; //Write 7 to variable
};
'>

3.3.2 Computed Signal Names

While accessing simulator variables, one can compute all or part of the signal name at run time by using the current value of an e variable inside parentheses. For example, in Figure 3-1, if there are three processors, processor_0, processor_1, and processor_2 instantiated inside top, it should be possible to pick out one of the three processor instances based on an e variable.

e allows the usage of many parentheses in the computation of a signal name. Thus, it is possible to dynamically choose the signal name at run time based on e variable values.

<'
struct driver{ //Struct in the e environment
id: uint(bits:2); //2 bit ID field determines processor 0,1,2
r_value: uint(bits:4); //Define a 4 bit field to read

read_value() is { //Define a method to read simulator
                  //variable
   r_value = '~/top/processor_(id)/FPU/add/operand';

   //If the id field == 1, then the above assignment
   //will be dynamically set to
   //r_value = '~/top/processor_1/FPU/add/operand';
};

'>
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