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The routing of IP traffic can be represented by two distinct planes of operation—the control plane and the data plane. The control plane deals with determining the information about where each destination IP address in the network is. Each destination IP address is associated with a next-hop IP address, which represents the next closest router to the destination. The data plane deals with the physical operations that are required to actually forward the packet to the next hop; this refers to the operation of storing the packet in memory while control plane information (such as the next hop address and egress interface) is determined, placing the appropriate Layer 2 addressing and encapsulation (depending on the egress interface Layer 2 protocol) on the frame, and then forwarding the packet out the appropriate egress interface to the next hop.

Layer 3 switching represents the data plane operations that are required to route IP traffic. Layer 3 switching can be performed in software, where an operating system application is responsible for the data plane operations, or in hardware, where a hardware chip (or ASIC) designed specifically for L3 switching is responsible for the data plane operations. Performing L3 switching in software allows for more flexibility because code can be written that uses as a common processor to perform the specific data plane operations required for each Layer 2 protocol. Performing L3 switching in hardware increases performance because all operations are performed by a function-specific chip, leaving the main processor free to perform other duties. Using hardware L3 switching is less flexible and more expensive because a hardware chip must be designed for each Layer 2 protocol (e.g., separate ASIC for Ethernet, separate ASIC for Token Ring).

Modern LAN design methodology recognizes the business requirements for the separation of functional groups within the LAN by using multiple VLANs. Separating functional groups increases network performance and efficiency and also allows for security access controls to be applied between each functional group (VLAN). From an IP perspective, each VLAN represents an IP subnet. For each IP subnet to communicate with remote IP subnets, IP routing or inter-VLAN routing is required. From a Layer 2 (Ethernet) perspective, IP routing is required between high-speed Ethernet networks which means that performance is a major consideration for inter-VLAN routing within the LAN. Hardware-based L3 switching within Ethernet LAN networks overcomes the performance limitations of software-based L3 switching and does not suffer the flexibility or cost disadvantages associated with hardware-based L3 switching, because only Ethernet-to-Ethernet L3 switching is required. This means only a single ASIC design is required.

Cisco Catalyst switches support two methods of hardware-based L3 switching. The methods differ in how the data plane components of L3 switching can get the necessary control plane information required to place in the Layer 2 framing. Multilayer switching (MLS) represents the first method of hardware-based L3 switching used by Cisco Catalyst switches and uses a flow-based model to populate a cache that includes the necessary control plane information for the data plane to L3 switch a packet. A flow simply represents a collection of IP packets that each shares a number of identical parameters, such as the same destination IP address or same destination TCP port. An MLS Route Processor (MLS-RP) provides control plane operations, while an MLS Switching Engine (MLS-SE) provides data plane operation. MLS requires that the first packet of a new flow (candidate packet) received by the MLS-SE be routed to the MLS-RP, which makes a control plane decision and routes the packet in software to its destination. The MLS-SE sees the control plane information in the return packet (enabler packet) that is sent to the destination and populates the MLS cache with the necessary control plane information required to L3 switch packets that belong to the flow. Subsequent packets received by the MLS-SE can be L3 switched in hardware without requiring the packet to be sent to the MLS-RP because the MLS cache includes the required control plane information.

The next-generation method of hardware-based L3 switching is based upon Cisco Express Forwarding (CEF). In the CEF architecture, the cache (that is used to store the necessary control plane information required for the data plane hardware ASICs to L3 switch each packet) is pre-populated with all the necessary control plane information (the CEF table). This means that the L3 switching ASIC can switch all IP packets in hardware, unlike MLS which requires the first packet of a flow to be switched in software (by the MLS-RP). This architecture is more efficient and scalable and resolves performance limitations of MLS in environments where thousands of new flows are established every second. The CEF architecture is also very easy to scale because CEF caching information can be distributed to multiple L3 switching ASICs. This means that a L3 switch can perform multiple L3 switching operations simultaneously—one per CEF cache and ASIC. The route processor (control plane) component of IP routing is responsible for generating the information in the CEF table and updating it as routing topology changes occur. The CEF table actually consists of two tables—the Forwarding Information Base (FIB) and the adjacency table.

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