Home > Store

Unabridged Pentium 4, The: IA32 Processor Genealogy

Register your product to gain access to bonus material or receive a coupon.

Unabridged Pentium 4, The: IA32 Processor Genealogy

Premium Website

  • Sorry, this book is no longer in print.
Not for Sale


  • Copyright 2005
  • Edition: 1st
  • Premium Website
  • ISBN-10: 0-321-24656-X
  • ISBN-13: 978-0-321-24656-1

“In this monumental new book, Tom Shanley pulls together 15 years of history of Intel’s mainline microprocessors, the most popular and important computer architecture in history. Shanley has a keen eye for the salient facts, and an outstanding sense for how to organize and display the material for easy accessibility by the reader. If you want to know what does this bit control, what does that feature do, and how did those instructions evolve through several generations of x86, this is the reference book for you. This is the book Intel should have written, but now they don’t have to.”

         —Bob Colwell, Intel Fellow

The Unabridged Pentium 4 offers unparalleled coverage of Intel’s IA32 family of processors, from the 386 through the Pentium 4 and Pentium M processors. Unlike other texts, which address solely a hardware or software audience, this book serves as a comprehensive technical reference for both audiences. Inside, Tom Shanley covers not only the hardware design and software enhancements of Intel’s latest processors, he also explains the relationship between these hardware and software characteristics. As a result, readers will come away with a complete understanding of the processor’s internal architecture, the Front Side Bus (FSB), the processor’s relationship to the system, and the processor’s software architecture.

Essential topics covered include:

  • Goals of single-task and multi-task operating systems
  • The 386 processor—the baseline ancestor of the IA32 processor family
  • The 486 processor, including a cache primer
  • The Pentium processor
  • The P6 roadmap, P6 processor core, and P6 FSB
  • The Pentium Pro processor, including the Microcode Update feature
  • The Pentium II and the Pentium II Xeon and Celeron processors
  • The Pentium III and the Pentium III Xeon and Celeron processors
  • The Pentium 4 processor family
  • The Pentium M processor
  • Processor identification, System Management Mode, and the IO and Local APICs

An “at-a-glance” table of contents allows readers to quickly find topics ranging from 386 Demand Mode Paging to Pentium 4 CPU Arbitration.

The accompanying CD-ROM contains 16 extra chapters.

Whether you design software or hardware or are responsible for system maintenance or customer support, The Unabridged Pentium 4 will prove an invaluable reference to the world’s most widely used microprocessor chips.

MindShare’s PC System Architecture series is a crisply written and comprehensive set of guides to the most important PC hardware standards. Books in the series are intended for use by hardware and software designers, programmers, and support personnel.

One of the leading technical training companies in the hardware industry, MindShare, Inc., provides innovative courses for dozens of companies, including HP, AMD, IBM, and Compaq. Through these classes and by writing the highly regarded PC System Architecture Series for Addison-Wesley, MindShare trainers emphasize the relationships of hardware subsystems to each other as well as the relationship between software and hardware.

Sample Content

Online Sample Chapter

How Multitasking Works at the Hardware Level

Downloadable Sample Chapter

Download the Sample Chapter related to this title.

Table of Contents

About This Book.

The IA32 Architecture Specification.

The Pentium® 4 Is the Sum of Its Ancestors.

The CD.

The MindShare Architecture Series.

Cautionary Note.

The Specification Is the Final Word.

Documentation Conventions.

Visit Our Web Site.

We Want Your Feedback.


1. Overview of the Processor Role.

The IA32 Specification.

IA32 Processors.

IA32 Instructions vs. μops.

Processor = Instruction Fetch/Decode/Execute Engine.

Some Instructions Result in FSB Transactions.

The Processor's Role in Today's Systems.

System Overview.


2. Single-Task OS and Application.

Operating System Overview.

Direct IO Access.

Application Program Memory Usage.

Task Initiation, Execution and Termination.

3. Definition of Multitasking.


An Example-Timeslicing.

Another Example-Awaiting an Event.

4. Multitasking Problems.

OS Protects Territorial Integrity.

Stay in Your Own Memory Area.

IO Port Anarchy.

Unauthorized Use of OS's Tools.

No Interrupts, Please!

BIOS Calls.

III. THE 386.

5. 386 Real Mode Operation.

Special Note.

An Overview of the 386 Internal Architecture.

An Overview of the 386DX FSB.

The 386 Register Set.

386 Power-Up State.

Initial Memory Reads.

IO Port Addressing.

Memory Addressing.

Real Mode Instructions and Registers.

Real Mode Interrupt/Exception Handling.

Protection in Real Mode.

6. Protected Mode Introduction.


Memory Protection.

IO Protection.

Privilege Levels.

Virtual 8086 Mode.

Task Switching.

Interrupt Handling.

7. Intro to Segmentation in Protected Mode.

Special Note.

Real Mode Limitations.

Segment Descriptor Describes a Memory Area in Detail.

Segment Register-Selects Descriptor Table and Entry.

Introduction to the Descriptor Tables.

General Segment Descriptor Format.

8. Code Segments.

Selecting the Code Segment to Execute.

Code Segment Descriptor Format.

Accessing the Code Segment.

Privilege Checking.

Calling a Procedure in the Current Task.

Call Gate.

9. Data and Stack Segments.

A Note Regarding Stack Segments.

The Data Segments.

Selecting and Accessing a Stack Segment.

10. Creating a Task.

What Is a Task?

Basics of Task Creation and Startup.

TSS Structure.

TSS Descriptor.

How the OS Starts a Task.

What Happens When a Task Starts.

Use of the LTR and STR Instructions.

11. Mechanics of a Task Switch.

Events that Initiate a Task Switch.

Switch Via a TSS Descriptor.

Task Gate Descriptor.

Task Switch Details.

Linked Tasks.

Linkage Modification.

The Busy Bit.

Address Mapping.

12. 386 Demand Mode Paging.

Problem-Loading Entire Task into Memory is Wasteful.

Solution-Load Part and Keep Remainder on Disk.

Problem-Running Two (or more) DOS Programs.

Solution-Redirect Memory Accesses to Separate Memory Areas.

Global Solution-Map Linear Address to Disk Address or to a Different Physical .

Memory Address.

The Paging Unit Is the Translator.

Three Possible Page Lookup Methods.

IA32 Page Lookup Method.

Enabling Paging.

Page Directory and Page Tables.

Finding the Location of a Physical Page.

Eliminating the Directory Lookup.

Checking Page Access Permission.

Page Faults.

Usage of the Dirty and Accessed Bits.

Demand Mode Paging Evolution.

13.The Flat Model.

Segments Complicate Things.

Paging Can Do It All.

Eliminating Segmentation.

The Privilege Check.

The Read/Write Check.

Each Task (including the OS) Has Its Own TSS.

14. Interrupts and Exceptions.

Special Note.


Hardware Interrupts.

Software-Generated Exceptions.

Interrupt/Exception Priority.

Real Mode Interrupt/Exception Handling.

Protected Mode Interrupt/Exception Handling.

Interrupt/Exception Handling in VM86 Mode.

Exception Error Codes.

The Resume Flag Prevents Multiple Debug Exceptions.

Special Case-Interrupts Disabled While Updating SS:ESP.

Detailed Description of the Software Exceptions.

15. Virtual 8086 Mode.

A Special Note.

DOS Application-Portrait of an Anarchist.

Solution-Set a Watchdog on the DOS Application.

The Virtual Machine Monitor (VMM).

Entering or Reentering VM86 Mode.

An Interrupt or Exception Causes an Exit From VM86 Mode.

A Task Switch Causes an EFlags Update.

DOS Task's Memory Usage.

The Privilege Level of a VM86 Task.

Restricting IO Accesses.

IOPL-Sensitive Instructions.

Interrupt/Exception Generation and Handling.

Registers Accessible in Real/VM86 Mode.

Instructions Usable in Real/VM86 Mode.

VM86 Mode Evolution.

16. The Debug Registers.

The Debug Registers.

IV. 486.

17. Caching Overview.

Definition of a Load and a Store.

The Cache's Purpose.

The Write-Through Cache.

The Write Back Cache.


The Overall Cache Architecture.

Cache Real Estate Management.

A Unified Cache.

Split Caches.

Non-Blocking Caches.

18. 486 Hardware Overview.

486 Flavors.

An Overview of the 486 Internal Architecture.

An Overview of the 486 FSB.

A20 Mask.

On-Chip Cache Added.

19. 486 Software Enhancements.

FPU Added On-Die.

Alignment Checking Feature.

Paging-Related Changes.

Caching-Related Changes to the Programming Environment.

CR4 Was Added in the Later Models of the 486.

Test Registers Added.

Instruction Set Changes.

New/Altered Exceptions.

System Management Mode (SMM).

V. Pentium®.

20. Pentium® Hardware Overview.

Pentium® Flavors.

An Overview of the Pentium® Internal Architecture.

An Overview of the Pentium® FSB.

The Caches.

Local APIC Added in the P54C.

Test Access Port (TAP).

FRC Mode.

Soft Reset (INIT#).

21. Pentium® Software Enhancements.

VM86 Extensions.

Protected Mode Virtual Interrupts.

Debug Extension.

Time Stamp Counter.

4MB Pages.

Machine Check Architecture (MCA).

Performance Monitoring.

Local APIC Register Set.

Test Registers Relocated.

MSRs Added.

Instruction Set Changes.

New/Altered Exceptions.


22. P6 Road Map.

The P6 Processor Family.

The Klamath Core.

The Deschutes Core.

The Katmai Core.

23. P6 Hardware Overview.

For More Detail.


The P6 Processor Core.

The FSB Interface Unit.

The Backside Bus (BSB) Interface Unit.

The Unified L2 Cache.

The L1 Data Cache.

The L1 Code Cache.

The Processor Core.

The Local APIC Unit.

VII. Pentium® Pro Software Enhancements.

24. Pentium® Pro Software Enhancements.

Paging Enhancements.

APIC Enhancements.

MMX Not Implemented.

SMM Enhancement.

MTRRs Added.

MCA Enhanced.

The Performance Counters.

MSRs Added.

Instruction Set Changes.

New/Altered Exceptions.

25. MicroCode Update Feature.

The Problem.

The Solution.

The Microcode Update Image.

Matching the Image to a Processor.

The Microcode Update Loader.

Updates in a Multiprocessor System.

The Image Management BIOS.

When Must the Image Upload Take Place?

Determining if a New Update Supersedes a Previously-Loaded Update.

Effect of RESET# Or INIT# on a Previously-Loaded Update.

VIII. Pentium® II.


The Pentium® Pro and Pentium® II: Same CPU, Different Package.

Dual-Independent Bus Architecture (DIBA).

IOQ Depth.

Pentium® Pro/Pentium® II Differences.

One Product Yields Three Product Lines.

The Pentium® II/Xeon/Celeron Roadmap.

The Cartridge.

The Core.

The FSB and BSB.

The Introduction of the Celeron.

Miscellaneous Hardware Stuff.

27. Pentium® II Power Management Features.

The Pentium® Pro's Power Conservation Modes.

The Pentium® II's Power Conservation Modes.

The Normal State.

The AutoHalt Power Down State.

The Stop Grant State.

The Halt/Grant Snoop State.

The Sleep State.

The Deep Sleep State.

28. Pentium® II Software Enhancements.

The Pentium® II and Pentium® III MSRs.

Instruction Set Changes.

New/Altered Exceptions.

29. Pentium® II Xeon Features.


To Avoid Confusion.

Basic Characteristics.

Hardware Characteristics.

PSE-36 Mode.


30. Pentium® III Hardware Overview.

One Product = Three Product Lines.

Pentium® II/Pentium® III Differences.

The Pentium® III/Xeon/Celeron Roadmap.

IOQ Depth.

The L1 Caches.

The L2 Cache.

The Data Prefetcher.

SSE Introduced.

The WCBs Were Enhanced.

Additional Writeback Buffers.

SpeedStep Technology.

31. Pentium® III Software Enhancements.

The Streaming SIMD Extensions (SSE).

CPUID Enhanced.

Serial Number Request Added.

Brand Index Request Added.

32. Pentium® III Xeon Features.

Basic Characteristics.

PAT Feature (Page Attribute Table).


33. Pentium® 4 Road Map.

The Roadmap.

34. Pentium® 4 System Overview.


The Graphics Adapter.

Device Adapters.


Definition of a Cluster.

Definition of the Boot Strap Processor.

Starting up the Application Processors (the APs).

35. Pentium® 4 Processor Overview.

The Pentium® 4 Processor Family.

Pentium® III/Pentium® 4 Differences.

Pentium® 4/Pentium® 4 Prescott Differences.

Pentium® 4 Processor Basic Organization.

The FSB is Tuned for Multiprocessing.

Intro to the FSB Enhancements.

IA Instructions Vary in Length and Are Complex.

The Trace Cache.

There Are Two Pipeline Sections.

The μop Pipeline.

The IA32 Data Register Set Was Small.

Speculative Execution.

36. Pentium® 4 PowerOn Configuration.

Configuration on Trailing-Edge of Reset.

Setup and Hold Time Requirements.

Built-In Self-Test (BIST) Trigger.

Assignment of IDs to the Processor.

Error Observation Options.

In-Order Queue Depth Selection.

Power-On Restart Address.

Tri-State Mode.

Processor Core Speed Selection.

Bus Parking Option.

Hyper-Threading Option.

Program-Accessible Startup Features.

37. Pentium® 4 Processor Startup.


The Processor's State After Reset.

EAX, EDX Content After Reset Removal.

The Core Is Starving and Caching is Disabled.

Boot Strap Processor (BSP) Selection.

How the APs are Discovered and Configured.

38. Pentium® 4 Core Description.

One μop Doesn't Necessarily = One IA32 Instruction.

Upstream vs Downstream.


The Big Picture.

The Front-End Pipeline Stages.

Intro to the μop Pipeline.

The μop Pipeline's Major Elements.

Additional, Core-Specific Terms.

39. Hyper-Threading.



The HT Approach.

Overview of HT Resource Usage.

HT and the Data TLB.

HT and the FSB.

The IOQ Depth Was Increased.

HT Performance Issues.

HT and Serializing Instructions.

HT and the Microcode Update Feature.

HT Cache-Related Issues.

HT and the TLBs.

HT and the Thermal Monitor Feature.

HT and External Pin Usage.

40. The Pentium® 4 Caches.

A Cache Primer.

The L0 Cache.

Upstream vs Downstream.


Determining the Processor's Cache Sizes and Structures.

Enabling/Disabling the Caches.

The L1 Data Cache.

The L2 ATC.

The L3 Cache.

FSB Transactions and the Caches.

The Cache Management Instructions.

41. Pentium® 4 Handling of Loads and Stores.

The Memory Type Defines Load/Store Characteristics.

Load μops.

Store-to-Load Forwarding.

Store μops.

The MFENCE Instruction.

Non-Temporal Stores.

42. The Pentium® 4 Prescott.


Increased Pipeline Depth.

Trace Cache Improvements.

Increased Number of WCBs.

L1 Data Cache Changes.

Increased L2 Cache Size.

Enhanced Branch Prediction.

Store Forwarding Improved.

SSE3 Instruction Set.

Increased Elimination of Dependencies.

Enhanced Shifter/Rotator.

Integer Multiply Enhanced.

Scheduler Enhancements.

Fixed the MXCSR Serialization Problem.

Data Prefetch Instruction Execution Enhanced.

Improved the Hardware Data Prefetcher.

Hyper-Threading Improved.

43. Pentium® 4 FSB Electrical Characteristics.


The Bus and Processor Clocks.

The Address and Data Strobes.

The Voltage ID.

Everything's Relative.

Signals that Can Be Driven by Multiple FSB Agents.

Minimum One BCLK Response Time.

44. Intro to the Pentium® 4 FSB.

Enhanced Mode Scaleable Bus.

FSB Agents.

Uniprocessor vs Multiprocessor Bus.

The Request Agent.

The Transaction Phases.

Transaction Pipelining.

Transaction Tracking.

45. Pentium® 4 CPU Arbitration.

The Request Phase.

Logical versus Physical Processors.

The Discussion Assumes a Quad Xeon MP System.

Symmetric Agent Arbitration-Democracy at Work.

46. Pentium® 4 Priority Agent Arbitration.

Priority Agent Arbitration.

47. Pentium® 4 Locked Transaction Series.


The Shared Resource Concept.

Testing the Availability of and Gaining Ownership of Shared Resources.

A Race Condition Can Present a Problem.

Guaranteeing the Atomicity of a Read/Modify/Write.

Locking a Cache Line.

48. Pentium® 4 FSB Blocking.

Blocking New Requests-Stop! I'm Full!

Assert BNR# When One Entry Remains.

BNR# Can Be Used by a Debug Tool.

Who Monitors BNR#?

BNR# is a Shared Signal.

The Stalled/Throttled/Free Indicator.

BNR# Behavior at Powerup.

BNR# Behavior During Runtime.

49. Pentium® 4 FSB Request Phase.

Cautionary Note.

Introduction to the Request Phase.

The Source Synchronous Strobes.

The Request Phase Parity.

Request Phase Parity Checking.

The Request Phase Signal Group is Multiplexed.

Introduction to the Transaction Types.

The Contents of Request Packet A.

The Contents of Request Packet B.

50. Pentium® 4 FSB Snoop Phase.

Agents Involved in the Snoop Phase.

The Snoop Phase Has Two Purposes.

The Snoop Result Signals are Shared, DEFER# Isn't.

The Snoop Phase Duration Is Variable.

There Is No Snoop Stall Duration Limit.

Memory Transaction Snooping.

Non-Memory Transactions Have a Snoop Phase.

51. Pentium® 4 FSB Response and Data Phases.

A Note on Deferred Transactions.

The Purpose of the Response Phase.

The Response Phase Signal Group.

The Response Phase Start Point.

The Response Phase End Point.

The Response Types.

The Response Phase May Complete a Transaction.

The Data Phase Signal Group.

Five Example Scenarios.

Data Phase Wait States.

The Response Phase Parity.

Data Bus Parity.

52. Pentium® 4 FSB Transaction Deferral.

Example System Models.

Example Multi-Cluster Model.

The Problem.

Possible Solutions.

Example Read From a PCI Express Device.

Example Write To a PCI Express Device.

Pentium® 4 Support for Transaction Deferral.

53. Pentium® 4 FSB IO Transactions.


The IO Address Range.

The Data Transfer Length.

54. Pentium® 4 FSB Central Agent Transactions.

Point-to-Point vs Broadcast.

The Interrupt Acknowledge Transaction.

The Special Transaction.

The BTM Transaction Is Used for Program Debug.

55. Pentium® 4 FSB Miscellaneous Signals.

The Signals.

56. Pentium® 4 Software Enhancements.

The Foundation.

Miscellaneous New Instructions.

Enhanced CPUID Instruction.

The SSE2 Instruction Set.

The SSE3 Instruction Set.

Local APIC Enhancements.

The Thermal Monitoring Facilities.

FPU Enhancement.

The MSRs.

The Machine Check Architecture.

Last Branch, Interrupt, and Exception Recording.

The Debug Store (DS) Mechanism.

New Exceptions.

The Performance Monitoring Facility.

57. Pentium® 4 Xeon Features.


The Pentium® 4 Xeon DP.

The Pentium® 4 Xeon MP.


58. Pentium® M Processor.


The Pentium® M and Centrino.

Characteristics Overview.

The FSB Characteristics.

Enhanced Power Management Characteristics.

Three Different Packaging Models.

Improved Thermal Monitor Mode.

Enhanced Branch Prediction.

μop Fusion.

Advanced Stack Management.


The Data Cache and Hyper-Threading.

The Next Pentium® M.


59. CPU Identification.

Prior to the Advent of the CPUID Instruction.

Determining if the CPUID instruction Is Supported.


Determining the Request Types Supported.

The Basic Request Types.

The Extended Request Types.

Enhanced Processor Signature.

60. System Management Mode (SMM).

What Falls Under the Heading of System Management?

The Genesis of SMM.

SMM Has Its Own Private Memory Space.

The Basic Elements of SMM.

A Very Simple Example Scenario.

How the Processor Knows the SM Memory Start Address.

Protected Mode, Paging and PAE-36 Mode Are Disabled.

The Organization of SM RAM.

Entering SMM.

Exiting SMM.

Caching from SM Memory.

Setting Up the SMI Handler in SM Memory.

Relocating the SM RAM Base Address.

SMM in an MP System.

61. The Local and IO APICs.

Before the Advent of the APIC.

MP Systems Need a Better Interrupt Distribution Mechanism.

A Short History of the APIC.

Detecting the Presence and Version of the Local APIC.

Enabling/Disabling the Local APIC.

Local Cluster and APIC ID Assignment.

An Introduction to the Interrupt Sources.

Introduction to Interrupt Priority.

An Intro to Edge-Triggered Interrupts.

An Intro to Level-Sensitive Interrupts.

The Local APIC Register Set.

Locally Generated Interrupts.

Task and Processor Priority.

Interrupt Messages.


Message Signaled Interrupts (MSI).

Message Format.

The Spurious Interrupt Vector.

The Agents in an Interrupt Message Transaction.

BSP Selection Process.

The APIC, the MPS and ACPI.




Download the Index file related to this title.


Submit Errata

More Information

InformIT Promotional Mailings & Special Offers

I would like to receive exclusive offers and hear about products from InformIT and its family of brands. I can unsubscribe at any time.


Pearson Education, Inc., 221 River Street, Hoboken, New Jersey 07030, (Pearson) presents this site to provide information about products and services that can be purchased through this site.

This privacy notice provides an overview of our commitment to privacy and describes how we collect, protect, use and share personal information collected through this site. Please note that other Pearson websites and online products and services have their own separate privacy policies.

Collection and Use of Information

To conduct business and deliver products and services, Pearson collects and uses personal information in several ways in connection with this site, including:

Questions and Inquiries

For inquiries and questions, we collect the inquiry or question, together with name, contact details (email address, phone number and mailing address) and any other additional information voluntarily submitted to us through a Contact Us form or an email. We use this information to address the inquiry and respond to the question.

Online Store

For orders and purchases placed through our online store on this site, we collect order details, name, institution name and address (if applicable), email address, phone number, shipping and billing addresses, credit/debit card information, shipping options and any instructions. We use this information to complete transactions, fulfill orders, communicate with individuals placing orders or visiting the online store, and for related purposes.


Pearson may offer opportunities to provide feedback or participate in surveys, including surveys evaluating Pearson products, services or sites. Participation is voluntary. Pearson collects information requested in the survey questions and uses the information to evaluate, support, maintain and improve products, services or sites, develop new products and services, conduct educational research and for other purposes specified in the survey.

Contests and Drawings

Occasionally, we may sponsor a contest or drawing. Participation is optional. Pearson collects name, contact information and other information specified on the entry form for the contest or drawing to conduct the contest or drawing. Pearson may collect additional personal information from the winners of a contest or drawing in order to award the prize and for tax reporting purposes, as required by law.


If you have elected to receive email newsletters or promotional mailings and special offers but want to unsubscribe, simply email information@informit.com.

Service Announcements

On rare occasions it is necessary to send out a strictly service related announcement. For instance, if our service is temporarily suspended for maintenance we might send users an email. Generally, users may not opt-out of these communications, though they can deactivate their account information. However, these communications are not promotional in nature.

Customer Service

We communicate with users on a regular basis to provide requested services and in regard to issues relating to their account we reply via email or phone in accordance with the users' wishes when a user submits their information through our Contact Us form.

Other Collection and Use of Information

Application and System Logs

Pearson automatically collects log data to help ensure the delivery, availability and security of this site. Log data may include technical information about how a user or visitor connected to this site, such as browser type, type of computer/device, operating system, internet service provider and IP address. We use this information for support purposes and to monitor the health of the site, identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents and appropriately scale computing resources.

Web Analytics

Pearson may use third party web trend analytical services, including Google Analytics, to collect visitor information, such as IP addresses, browser types, referring pages, pages visited and time spent on a particular site. While these analytical services collect and report information on an anonymous basis, they may use cookies to gather web trend information. The information gathered may enable Pearson (but not the third party web trend services) to link information with application and system log data. Pearson uses this information for system administration and to identify problems, improve service, detect unauthorized access and fraudulent activity, prevent and respond to security incidents, appropriately scale computing resources and otherwise support and deliver this site and its services.

Cookies and Related Technologies

This site uses cookies and similar technologies to personalize content, measure traffic patterns, control security, track use and access of information on this site, and provide interest-based messages and advertising. Users can manage and block the use of cookies through their browser. Disabling or blocking certain cookies may limit the functionality of this site.

Do Not Track

This site currently does not respond to Do Not Track signals.


Pearson uses appropriate physical, administrative and technical security measures to protect personal information from unauthorized access, use and disclosure.


This site is not directed to children under the age of 13.


Pearson may send or direct marketing communications to users, provided that

  • Pearson will not use personal information collected or processed as a K-12 school service provider for the purpose of directed or targeted advertising.
  • Such marketing is consistent with applicable law and Pearson's legal obligations.
  • Pearson will not knowingly direct or send marketing communications to an individual who has expressed a preference not to receive marketing.
  • Where required by applicable law, express or implied consent to marketing exists and has not been withdrawn.

Pearson may provide personal information to a third party service provider on a restricted basis to provide marketing solely on behalf of Pearson or an affiliate or customer for whom Pearson is a service provider. Marketing preferences may be changed at any time.

Correcting/Updating Personal Information

If a user's personally identifiable information changes (such as your postal address or email address), we provide a way to correct or update that user's personal data provided to us. This can be done on the Account page. If a user no longer desires our service and desires to delete his or her account, please contact us at customer-service@informit.com and we will process the deletion of a user's account.


Users can always make an informed choice as to whether they should proceed with certain services offered by InformIT. If you choose to remove yourself from our mailing list(s) simply visit the following page and uncheck any communication you no longer want to receive: www.informit.com/u.aspx.

Sale of Personal Information

Pearson does not rent or sell personal information in exchange for any payment of money.

While Pearson does not sell personal information, as defined in Nevada law, Nevada residents may email a request for no sale of their personal information to NevadaDesignatedRequest@pearson.com.

Supplemental Privacy Statement for California Residents

California residents should read our Supplemental privacy statement for California residents in conjunction with this Privacy Notice. The Supplemental privacy statement for California residents explains Pearson's commitment to comply with California law and applies to personal information of California residents collected in connection with this site and the Services.

Sharing and Disclosure

Pearson may disclose personal information, as follows:

  • As required by law.
  • With the consent of the individual (or their parent, if the individual is a minor)
  • In response to a subpoena, court order or legal process, to the extent permitted or required by law
  • To protect the security and safety of individuals, data, assets and systems, consistent with applicable law
  • In connection the sale, joint venture or other transfer of some or all of its company or assets, subject to the provisions of this Privacy Notice
  • To investigate or address actual or suspected fraud or other illegal activities
  • To exercise its legal rights, including enforcement of the Terms of Use for this site or another contract
  • To affiliated Pearson companies and other companies and organizations who perform work for Pearson and are obligated to protect the privacy of personal information consistent with this Privacy Notice
  • To a school, organization, company or government agency, where Pearson collects or processes the personal information in a school setting or on behalf of such organization, company or government agency.


This web site contains links to other sites. Please be aware that we are not responsible for the privacy practices of such other sites. We encourage our users to be aware when they leave our site and to read the privacy statements of each and every web site that collects Personal Information. This privacy statement applies solely to information collected by this web site.

Requests and Contact

Please contact us about this Privacy Notice or if you have any requests or questions relating to the privacy of your personal information.

Changes to this Privacy Notice

We may revise this Privacy Notice through an updated posting. We will identify the effective date of the revision in the posting. Often, updates are made to provide greater clarity or to comply with changes in regulatory requirements. If the updates involve material changes to the collection, protection, use or disclosure of Personal Information, Pearson will provide notice of the change through a conspicuous notice on this site or other appropriate way. Continued use of the site after the effective date of a posted revision evidences acceptance. Please contact us if you have questions or concerns about the Privacy Notice or any objection to any revisions.

Last Update: November 17, 2020