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HyperTransport System Architecture

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HyperTransport System Architecture

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Description

  • Copyright 2003
  • Edition: 1st
  • Book
  • ISBN-10: 0-321-16845-3
  • ISBN-13: 978-0-321-16845-0

PCI was originally designed to be used in a wide range of systems from notebooks to high-end servers. There are now a wide range of new buses being developed to replace PCI, which enable cost-savings, performance enhancement, and specialized features. HyperTransport is a new bus that deals specifically with chipset interconnect, the high-speed link between the memory and IO controller chips. HyperTransport Architecture allows hardware and low-level software designers, engineers, and technicians to get up to speed quickly on this new bus protocol, without having to wade through specifications and white papers. The book organizes topics in a logical, tutorial format which quickly guides the reader through the major features of the specification. Numerous diagrams and examples reduce the more complicated concepts to manageable proportions and allow the reader to see the important relationships along the way.

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HyperTransport Flow Control

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Table of Contents



About This Book.

I. OVERVIEW OF HYPERTRANSPORT.

Introduction to HyperTransport.
HT Architectural Overview.

II. HYPERTRANSPORT CORE TOPICS.

Signal Groups.
Packet Protocol.
Flow Control.
IO Ordering.
Transaction Examples.
HT Interrupts.
System Management.
Error Detection And Handling.
Routing Packets.
Reset & Initialization.
Device Configuration.
Electrical.
Clocking.

III. HYPERTRANSPORT OPTIONAL TOPICS.

HyperTransport Bridges.
Double-Hosted Chains.
HT Power Management.
Networking Extensions.

IV. HYPERTRANSPORT LEGACY SUPPORT.

I/O Compatibility.
Address Remapping.
X86 CPU Compatibility.
Appendix.
Glossary.
Index. 0321168453T11262002.

Preface

Cautionary Note

The reader should keep in mind that MindShare's book series often details rapidly evolving technologies. The being the case, it should be recognized that the book is a "snapshot" of the state of the technology at the time the book was completed. We make every attempt to produce our books on a timely basis, but the next revision of the specification is not introduced in time to make necessary changes. This HyperTransport book complies with revision 1.04 of the Hyper-Transport™ I/O Link specification. The Networking Extensions specification was still under development and not released when this book was completed. However, a chapter covering the major features of the Networking Extensions specification has been included in this book.

Intended Audience

This book is intended for use by hardware and software design and support personnel. The tutorial approach taken may also make it useful to technical personnel not directly involved design, verification, and other support functions.

Prerequisite Knowledge

It is recommended that the reader has a reasonable background in PC architecture, including experience or knowledge of an I/O bus and related protocol. The MindShare publications entitled ISA System Architecture focusses on various aspects of PCI architecture and provides the necessary background.

Topics and Organization

Topics covered in this book and the flow of the book are as follows:

Part 1: Overview of HyperTransport™ Technology
Chapter 1: Introduction to HyperTransport™
Chapter 2: Big Picture
Part 2: HyperTransport™ Core Topics
Chapter 3: Signal Groups
Chapter 4: Packet Protocol
Chapter 5: Flow Control
Chapter 6: Transaction Ordering
Chapter 7: Transaction Examples
Chapter 8: HyperTransport Interrupts
Chapter 9: System Management
Chapter 10: Error Detection and Handling
Chapter 11: Routing Packets
Chapter 12: Reset and Initialization
Chapter 13: Device Configuration
Chapter 14: Electrical Implementation
Chapter 15: Clocking Concepts
Chapter 16: HyperTransport Bridges
Part 3: HyperTransport™ Optional Topics
Chapter 17: HyperTransport Bridges
Chapter 18: Double-Hosted Chains
Chapter 19: Power Management
Chapter 20: Networking Extensions
Part 4: HyperTransport Legacy Support
Chapter 21: I/O Compatibility
Chapter 22: Address Remapping
Chapter 23: x86 CPU Compatibility
Appendix: Glossary
Index
Documentation Conventions

This section defines the typographical convention used throughout this book.

HyperTransport™

HyperTransport™ is a trademark of the HyperTransport Consortium. This book takes the liberty of abbreviating HyperTransport as "HT." to improve readability.

Hexadecimal Notation

All hex numbers are followed by a lower case "h." For example:
89F2BD02h
0111h

Binary Notation

All binary numbers are followed by a lower case "b." For example:
1000 1001 1111 0010b
01b

Decimal Notation

Number without any suffix are decimal. When required for clarity, decimalnumbers are followed by a lower case "d." Examples:
9
15
512d

Bits Versus Bytes Notation

This book represents bit with lower case "b" and bytes with an upper case "B." For example:
Megabits/second = Mb/s
Megabytes/second = MG/s

Bit Fields and Groups of Signals

Groups of signals or bits are represented with the high-order bits first followed by the low-order bits and enclosed by brackets. For example:
7:0
Addr39:0
CAD15:0

Active Signal States

Signals that are active low are followed by #, as in RESET#. Active high signals have no suffix following the signal, as in PWROK.

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0321168453P11262002

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