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New Techniques and Tools for Ensuring On-Chip Power Integrity—Down to NanoscaleAs chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem solving.
Raj Nair and Dr. Donald Bennett first provide a complete foundational understanding of power integrity, including ULSI issues, practical aspects of power delivery, and the benefits of a total power integrity approach to optimizing chip physical designs. They introduce advanced power distribution network modeling, design, and analysis techniques that highlight abstraction and physics-based analysis, while also incorporating traditional circuit- and field-solver based approaches. They also present advanced techniques for floorplanning and power integrity management, and help designers anticipate emerging challenges associated with increased integration. Anasim RLCSim.exe, a new tool for power integrity aware floorplanning, is downloadable for free at anasim.com/category/software.
The authors
Power Integrity Analysis and Management for Integrated Circuits’ coverage of both fundamentals and advanced techniques will make this book indispensable to all engineers responsible for signal integrity, power integrity, hardware, or system design—especially those working at the nanoscale level.
Preface xv
Acknowledgments xxi
About the Authors xxiii
Contributors xxv
Chapter 1: Power, Delivering Power, and Power Integrity 1
1.1 Electromotive Force (emf) 1
1.2 Electrical Power 5
1.3 Power Delivery 8
1.4 Power Integrity (PI) 13
1.5 Exercises 17
References 18
Chapter 2: Ultra-Large-Scale Integration and Power Challenges 19
2.1 Exponential Integration and Semiconductor Scaling 20
2.2 Power and Energy Consumption 27
2.3 Power, Heat, and Power Integrity Challenges 39
2.4 Exercises 50
References 51
Chapter 3: IC Power Integrity and Optimal Power Delivery 53
3.1 Power Transfer and Efficiency 53
3.2 Optimal IC Power Delivery: On-Chip Inductance and Grid Design 81
3.3 Power Grid Cost Factor Trade-off Analysis and Design 99
3.4 Exercises 106
References 107
Chapter 4: Early Power Integrity Analysis and Abstraction 111
4.1 Process, Voltage, and Temperature: Design Verification Space 112
4.2 Back-End and Front-End PI Analysis 115
4.3 Simulation Environment for Models of High Abstraction Levels 126
4.4 Abstraction and PI Analysis Examples 129
4.5 Summary and Enhancements 135
4.6 Exercises 136
References 138
Chapter 5: Power Integrity Analysis and EMI/EMC 141
5.1 Introduction 141
5.2 Analysis of Noise Generation and Propagation through a Power Distribution Network 143
5.3 Modeling Decoupling Capacitors for Noise Mitigation in PDNs 150
5.4 Current Design Methodology for Power Delivery Networks 154
5.5 Modeling Methodologies 159
5.6 Numerical Methods 169
5.7 Power and Signal Delivery Analysis Tools and Limitations 176
5.8 Power Integrity-Aware Electromagnetic Interference Analysis 188
5.9 Strengths and Limitations of Existing Early EMI m
