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MIPS R4000 User's Manual

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MIPS R4000 User's Manual


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  • covers the latest advances in:
    • 64-bit memory management

    • 64-bit Floating Point Unit Operations

    • R4000 signal descriptions — boot end initialization interface; clock signals and interface

    • System Cache description and organization

    • Secondary Cache interface

    • multiprocessor cache coherency mechanisms

    • operation end timing diagrams of the System interface

    • error checking and correcting (ECC)


  • Copyright 1993
  • Dimensions: 7" x 9-1/4"
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-105925-4
  • ISBN-13: 978-0-13-105925-2

This manual is a comprehensive reference describing the implementation-specific interfaces and architectural features of the highly-integrated 64-bit R4000 and R4400 MIPS RISC processors. This manual also describes the MIPS RISC instruction Set Architecture (ISA), including the 64-bit extensions of the ISA.

Sample Content

Table of Contents

 1. Introduction.

 2. CPU Instruction Set Summary.

 3. The CPU Pipeline.

 4. Memory Management.

 5. CPU Exception Processing.

 6. Floating-Point Unit.

 7. Floating-Point Exceptions.

 8. R4000 Processor Signal Descriptions.

 9. Initialization Interface.

10. Clock Interface.

11. Cache Organization, Operation, and Coherency.

12. System Interface.

13. Secondary Cache Interface.

14. JTAG Interface.

15. R4000 Processor Interrupts.

16. Error Checking and Correcting.

Appendix A: CPU Instruction Set Details.

Appendix B: FPU Instruction Set Details.

Appendix C: Subblock Ordering.

Appendix D: Output Buffer …Di/…Dt Control Mechanism.

Appendix E: PLL Passive Components.

Appendix F: R4000 Coprocessor 0 Hazards.


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