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This chapter is from the book

This chapter is from the book

8.3 Cell Placement

The SoC block designer relies on the (timing-driven) cell placement flow to provide a routable solution with minimal timing issues for a netlist with (tens of) millions of instances. Placement algorithms have evolved to provide greater netlist capacity with reasonable runtime. To help physical designers achieve improved predictability and confidence in timing closure, the EDA vendor placement tools have incorporated additional features that apply input constraints:

  • Preplaced cells and hard IP macros

  • Relative placement groups of cells (a set of cells with relative alignment coordinates that are placed/moved as a unit)

  • Restrictive area allocation within the floorplan block for subsets of the cell netlist (see Figure 8.2)

    FIGURE 8.2

    Figure 8.2 The block placement flow may be provided with restricted areas for placement of subsets of the block netlist cells. This subset would typically be identified by a specific string in the (flattened netlist hierarchy) instance name.

  • Guidelines for maximum local cell utilization percentage (to allow for the addition of a suitable density of decoupling capacitance cells, substrate and well contact cells, and dummy logic cells for ECOs)

  • Ability to place cells with cell height that spans two rows of the placement image (see Figure 8.3)

FIGURE 8.3

Figure 8.3 The cell library may contain physical cells spanning two rows in height.

For current fabrication process nodes, additional cell adjacency restrictions must be observed during placement. Lithographic uniformity of (critical dimension) device gates may require the insertion of dummy gates between cells and at the ends of cell rows. The transition between cells of different Vt types may also require dummy gate cells to reduce the device variation from Vt mask overlay and implant dosage. Depending on the design of the cell image, the placement algorithm may also need to insert device well continuity filler cells in vacant locations. The methodology team needs to review the cell library techfile data and fabrication process design rules to ensure that any specific placement restrictions and/or dummy cell insertion guidelines are coded for the EDA placement tool.

Throughout the evolution of EDA placement tools, the goal has consistently been to provide a result that is ultimately routable and achieves timing targets, with runtimes that scale with the increasing block netlist instance size. Prior to the introduction of physical synthesis, placement tools consisted of constructive cell/macro location assignment followed by iterative optimization (or “successive refinement”) steps. The physical synthesis methodology has resulted in a shift in EDA placement tool development emphasis to improving the iterative solutions. Numerous algorithms have been developed to select candidate cells to reposition and evaluate new proposed locations and/or to successively resolve placement overlaps from an existing assignment, with optimization objectives that address routing congestion and estimated path timing improvements.[1, 2]

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