8.2 Parasitic Interconnect Estimation
The placement flow utilizes a number of measurement criteria when selecting a candidate location for each cell or for candidate pairs of cells to swap their current coordinates. The process involves a combination of geometric and timing-driven calculations, including the following:
Total estimated network wire length to realize all connections, using one of various net topology estimates (e.g., bounding box, star, Steiner tree) (Timing estimates from physical synthesis provide [negative slack] nets that may be given additional weighting in the total geometric wire length summation calculation.)
Interconnect segments crossing a coarse grid overlay of the block floorplan to assess wiring track demand versus availability (to avoid congestion)
Cell interconnect delay calculation for timing-driven placement optimization
The representation of interconnect delays during placement involves estimates of the R*C parasitics and a simplified computationally fast delay calculation algorithm (e.g., an Elmore delay model for the estimated net topology; see Section 11.1). The SoC methodology team needs to collaborate with the EDA vendor and the foundry to determine how to best estimate the interconnect parasitic delay during cell placement. This estimate needs to reflect the different (per unit length) R and C measures of the multiple horizontal and vertical metal routing layers available within the block. During cell placement, an average R*C delay measure across the available metal routing layers is used. An estimate for parasitic via resistances could also be included in the interconnect delay model.
In addition, the methodology team may use the physical synthesis timing data to derive “non-default” constraints for subsequent cell placement and routing:
Preferred metal layers for routing critical nets
Wider width segments (e.g., 1.5X or 2X width rather than 1X)
The EDA placement tool applies a different set of parasitic interconnect estimates for nets with non-default rules. Again, collaboration with the EDA vendor and foundry is required to define how multiple wire load models for different classes of nets should be calculated for timing-driven placement optimizations.