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This chapter is from the book

This chapter is from the book

Intel Xeon DP and Xeon MP Chipsets

The Intel Xeon DP and Xeon MP processors are workstation and server-class processors based on the Pentium 4 processor, but they use a larger socket (Socket 603/604) and use the E75xx series of chipsets. The E75xx chipsets are improved versions of the 860 chipset, which was the first Xeon DP chipset.

The Intel 860 Chipset

The Intel 860 was a high-performance chipset designed for the first Socket 603 (Pentium 4–based) Xeon processors for DP workstations. The 860 uses the same ICH2 as the Intel 850 but uses a different MCH—the 82860, which supports one or two Socket 603 ("Foster") Xeon processors. The other major features of the 82860 are similar to those of the 82850, including support for dual 400MHz RDRAM memory channels with a 3.2GBps bandwidth and a 400MHz system bus. The 82860 MCH also supports 1.5V AGP 4x video cards at a bandwidth exceeding 1GBps.

The 860 chipset uses a modular design, in which its two core chips can be supplemented by the 82860AA (P64H) 66MHz PCI controller hub and the 82803AA MRHR. The 82860AA supports 64-bit PCI slots at either 33MHz or 66MHz, and the 82803AA converts each RDRAM memory channel into two, which doubles memory capacity. Thus, whether a particular 860-based motherboard offers 64-bit or 66MHz PCI slots or dual-channel RDRAM memory depends on whether these supplemental chips are used in its design.

The 860 chipset was replaced by the E7500 Plumas chipset in 2002.

The Intel E7500 Chipset

The Intel E7500 chipset, codenamed Plumas, was introduced in March 2002. It supports up to two Xeon processors with 512KB L2 cache, 400MHz FSB, and Intel HT Technology. The E7500's design is simpler than that used by the 860 because by 2002, Intel was no longer supporting RDRAM in new systems.

The E7500 chipset includes the MCH and the ICH3-S ICH. To achieve 66MHz/64-bit PCI and 133MHz PCI-X support, the E7500 can be used with up to three optional P64H2 (82870P2) chips, an improved version of the P64H chip that is an optional part of the 860 chipset. Note that the E7500's MCH connects directly to memory, rather than to MRHR chips as with the 860. The E7500's design is simpler than that used by the 860, because by 2002 Intel was no longer supporting RDRAM in new systems. The E7500 supports up to 16GB of dual-channel DDR200 registered ECC SDRAM memory (up to eight modules). Its Intel x4 single-device data correction (SDDC) can correct up to four errors per memory module for better system reliability. Hub Architecture 2.0 provides a 2GBps bidirectional connection between the E7500 MCH and each P64H2 chip.

The E7500, and its sibling, the E7501 (described in the next section), have been used in many two-way servers.

The Intel E7501 Chipset

The Intel E7501 chipset, codenamed Plumas 533, was introduced in November 2002. It represents an improved version of the E7500, differing primarily in support for the 533MHz FSB versions of Xeon processors and support for dual-channel DDR266 memory. The E7501 also uses the same P64H2 and ICH-3S chips as the E7500.

Figure 3.17 depicts the architecture of the E7501 chipset.

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Figure 3.17 The E7501 is a faster version of the E7500; both support two Xeon processors.

The Intel E7505 Chipset

The Intel E7505 chipset, codenamed Placer, was introduced in November 2002. It supports up to two Xeon processors with 512KB L2 cache, 533MHz FSB, and Intel HT Technology.

The E7505 supports 1.5V AGP 1x–8x and AGP Pro cards (but not the nonstandard 3.5V versions of AGP once sold by some vendors), and it uses the ICH4. To achieve 66MHz/64-bit PCI and 133MHz PCI-X support, the E7505 can be used with up to three optional P64H2 (82870P2) chips. The E7505 uses the ICH4. The E7505 has been used in many two-way server and workstation designs.

Figure 3.18 illustrates the architecture of the E7505 chipset.

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Figure 3.18 The E7505 supports AGP 8x, making it suitable for workstation as well as server applications.

The Intel E7520 and E7320 Chipsets

The Intel E7520 chipset, codenamed Lindenhurst, was introduced in August 2004. Its companion, the E7320 chipset, codenamed Lindenhurst VS, was introduced at the same time. Both chipsets support up to two 64-bit (EM64T) Xeon processors with 2MB L2 cache, 800MHz FSB, and Intel HT Technology or Xeon processors with 1MB L2 cache and 800MHz FSB.

These chipsets support dual-channel DDR2-400 or DDR 333/266 memory and can be used with either the ICH5R or 6300ESB ICHs.

The E7520 differs from the less-expensive E7320 by offering memory mirroring as well as DMA support in the memory subsystem. Both chipsets support ECC memory, X4 SDDC, and hub interface ECC for reliable memory access.

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See "Advanced Error Correction Technologies," p. 391.

The E7520 includes three PCI-Express x8 interfaces, and the E7320 includes one PCI-Express x8 interface. The x8 interfaces can be configured as two PCI-Express x4 interfaces, which act as hosts for optional 6700 PXH 64-bit PCI hubs that provide 66MHz PCI-X or PCI interfaces with hot-plug support. The E7520 also supports the IOP332 I/O processor chip (codenamed Dobson), designed for high-performance RAID implementations. Figure 3.19 illustrates a typical block diagram for a system running an E7520/6300ESB chipset.

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Figure 3.19 The E7520 supports PCI-X and PCI-Express interfaces, enabling it to operate with the latest high-speed I/O boards for SCSI RAID, networking, and other applications.

The Intel E8500 Chipset

The Intel E8500 chipset, codenamed Twin Castle before its release, was introduced in April 2005. It supports up to four of the latest dual-core Xeon MP processors as well as existing single-core processors, and it supports Intel's EM64T extensions, enabling this chipset to support 64-bit or 32-bit server operating systems. When dual-core Xeon MP processors are used, the system is essentially an eight-way system.

The E8500 chipset includes the following components:

  • E8500 North Bridge
  • E8500 XMB
  • 6700PXH 64-bit PCI hub (supports PCI and PCI-X slots up to 133MHz)
  • ICH5 (equivalent to the South Bridge)

Despite Intel's use of the term "North Bridge," the E8500 uses a hub architecture to connect to the ICH5.

The E8500 North Bridge supports PCI-Express, providing three x8 lanes and four 1x lanes. PCI-Express support enables the E8500 to use newly emerging and forthcoming PCI-Express interfaces for high-speed networking, SCSI RAID arrays, and other server-optimized components.

The E8500 supports DDR266, DDR333, and DDR-2 400 memory via one or more high-speed IMI connections to the 8500's XMB memory bridge chips (see Figure 3.20). It supports registered ECC DIMMS and features memory RAID (similar to memory mirroring) and demand and patrol scrubbing to detect and repair memory problems. If it encounters a memory problem that cannot be repaired, it marks the bad location so that it will not be used in the future. The IMI interconnect runs at 2.67GBps inbound and 5.33GBps outbound.

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Figure 3.20 The E8500 combines the hub architecture of the 8xx-series chipsets with specialized memory controller and PCI-Express bridge chips to support a powerful four-way architecture.

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