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This chapter is from the book

1.5 The Bottom Line

  1. The PDN consists of all the interconnects from the pads on the die to the VRM and all of the components in between.

  2. The purpose of the PDN is to provide a clean, low-noise voltage and ground supply to the devices and a low impedance return path for signals, and to mitigate EMC problems.

  3. The typical noise spec on the PDN of 5% tolerance is based on an allocation of 1/3 the noise budget to each of the main sources of noise: reflection noise, cross talk, and PDN.

  4. Voltage noise on the PDN is a result of transient power currents passing through the impedance of the PDN. The amount of noise is due to the combination of the impedance profile and the transient current spectrum.

  5. Noise on the PDN can contribute to jitter. A typical value of the sensitivity is 1 psec/mV of noise. This number varies depending on the chip design and device technology node.

  6. The impedance profile, as applied to the chip pads, is the most important metric for the quality and performance of the PDN. This is from DC to the highest frequency components of the switching signals.

  7. The target impedance is a measure of the maximum impedance, which will keep the worst-case voltage noise below the acceptable spec.

  8. The PDN ratio is the ratio of the actual PDN peak impedance to the target impedance. It is a good metric of risk. A PDN ratio greater than 10 is a high-risk design.

  9. Sculpting the impedance profile requires optimizing both the individual elements of the PDN and their interactions. The entire PDN ecology must be optimized to reduce the peak values.

  10. If you care about PDN design, this book is for you.

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