- 1.1 What Is the Power Delivery Network (PDN) and Why Should I Care?
- 1.2 Engineering the PDN
- 1.3 "Working" or "Robust" PDN Design
- 1.4 Sculpting the PDN Impedance Profile
- 1.5 The Bottom Line

## 1.3 “Working” or “Robust” PDN Design

The variability in performance due to the specific microcode driving the switching of on-die gates makes testing a product for adequate PDN design difficult. A product might work just fine at boot up, or when running a specific software test suite if the combination of current spectral peaks and impedance peaks results in less than the specified transient noise. The product design may “pass” this test and be stamped as “working.”

However, if another software suite were to run that drives more gates and causes them to switch at a different dominant loop frequency, which coincidently overlaps a peak in the PDN impedance profile, larger instantaneous voltage drops might result and the same product could fail.

Although having the product boot up, run a test suite and apparently work is encouraging, it does not guarantee “robust” operation. Products often “work” in evaluation but have field failures when driven by a broad range of customer software.

A robust PDN design means that any software code may run and generate the maximum transient current at any arbitrary frequency with any time domain signature. The resulting worst-case voltage generated by this current through the impedance profile is always less than an amount that would cause a failure.

The combination of the worst-case transient current and the voltage noise specification work together to set a limit for the maximum allowable PDN impedance such that the voltage noise will never exceed the specification.

This maximum allowable PDN impedance with guaranteed performance is referred to as the *target impedance* in PDN design, and we derive it with [1]

where

Z

_{target}= the maximum allowable PDN impedance at any frequencyΔV

_{noise}= the maximum specified voltage rail noise to meet performance requirementsI

_{max-transient}= the worst-case transient current under any possible operation

For example, if the noise spec is set as ±50 mV and the worst-case transient current is 1 A, the target impedance is

If either ΔV_{noise} or I_{max-transient} is a function of frequency, then Z_{target} is a function of frequency.

In principle, the combination of the entire spectral distribution of currents and the entire impedance profile is what creates the worst-case peak voltage noise. Unfortunately, this can only be determined with a transient simulation including the details of the transient current waveform and the impedance profile of the entire PDN. In practice, the target impedance is a useful approximation as a figure of merit to help focus the design of the PDN on a good starting place.

A fully robust PDN is defined by this target impedance. If the impedance of the entire PDN ecology, as applied to the pads of the die, is below the target impedance at all frequencies, the maximum worst-case rail collapse noise generated by the transient current flowing through the PDN impedance will not exceed the noise spec except in a very rare rogue wave situation. Figure 1.6 shows an example of the impedance profile below the target impedance of 50 mΩ at all frequencies and an example of the resulting rail voltage noise with a high current load.

**Figure 1.6** ** Top:** The impedance profile of the PDN ecology engineered to be below the target impedance from DC up to a very high bandwidth.

**The resulting Vdd rail noise under large transient current load showing the noise is always below the 5% spec limit. The square wave trace is the transient current as driven by a clock. It is plotted on a relative scale.**

*Bottom:*In practice, the maximum, worst-case transient current through the die will not be flat at all frequencies. The maximum current amplitude generally drops off at the high-frequency end, related to how quickly the maximum number of switching gates can be turned on. The precise details depend on the chip architecture, the number of bits in the pipeline, and the nature of the microcode. The effective rise time could be from the rise time of the clock edge to 100 clock cycles.

For example, if the clock frequency is 2 GHz, with a 0.5 ns clock period, and the maximum number of switching gates requires 20 cycles to build up, the shortest rise time for the turn on of the worst-case transient current would be 0.5 ns × 20 cycles = 10 ns. The amplitude of the maximum transient current frequency components will begin to roll off above about 0.35/10 ns = 35 MHz. Above 35 MHz, the worst-case transient current spectrum would drop off at −20 dB/decade and the resulting target impedance would increase with frequency. The target impedance, in this example, assuming a 50 mV rail voltage noise spec and worst-case current amplitude of 1 A, is shown in Figure 1.7.

**Figure 1.7** Target impedance when the transient current turns on in 20 clock cycles to a maximum of 1 A.

The consequence of this behavior is that the target impedance spec is relaxed at higher frequency. Estimating where this knee frequency begins is often difficult unless we know the details of the transient current and worst-case microcode.

This analysis points out that, in practice, accurately calculating the transient currents and the precise requirements for the target impedance of the PDN is extremely difficult. One must always apply engineering judgment in translating the information available into the requirements for a cost-effective design.

The process to engineer the PDN is to

Establish a best guess for the target impedance based on what is known about the functioning and applications of the chips.

Make engineering decisions to try to meet this impedance profile where possible.

Balance the trade-offs between the cost of implementing the PDN impedance compared to the target impedance, and the risk of a field failure.

A rough measure of the risk of a failure of circuits to run at rated performance is the ratio of the actual PDN impedance to the target impedance, termed the *PDN ratio*:

A ratio of less than 1 indicates low risk of a PDN-related failure. As this ratio increases, the risk increases as well. From practical experience, a ratio of 2 might still offer an acceptable risk, but a ratio of 10 will almost surely result in unacceptable risk. Even though many microcodes run at rated performance, some are likely to stimulate the PDN resonance and generate product stability issues.

Generally, achieving a lower impedance PDN, and consequently a lower risk ratio, costs more either due to more components required, tighter assembly design rules impacting yield, more layers in the board or package, increased area for die capacitance, or the use of more expensive materials. The balance between cost and risk is often a question of how much risk you are comfortable with. By paying more for added design margin, you can always “buy insurance” and reduce the risk. This is the fundamental trade-off in PDN design.

In consumer applications, often strongly cost driven, engineering for a higher risk ratio with a lower cost design might be a better balance. However, in avionic systems, for example, paying extra for a risk ratio less than 1 might be the cost-effective solution. Different applications have a different balance between cost and risk ratio.