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This chapter is from the book

1.2 Engineering the PDN

To meet both voltage noise and the timing budgets, the voltage noise on the PDN must be kept below some specified value. Depending on the system details, this voltage noise limit is roughly about ±5% of the supply voltage. In typical CMOS-based digital systems with single-ended signals, the total noise margin for the receiver is about 15% of the signal swing. Unless there is a compelling reason not to do so, we usually partition this budget equally between the three dominate sources of noise: reflection noise, crosstalk, and PDN noise. This is the origin of the typical specification being 5% PDN noise allowed.

In some applications, such as analog-to-digital converters (ADCs) or phase locked loops (PLLs), performance is very sensitive to voltage noise and the PDN noise must be kept below 1%. The voltage noise must be kept below the limits from DC all the way up to the bandwidth of the signals, which might be as high as 5 GHz to 10 GHz.

As with all signal integrity problems, the first step in eliminating them is to identify the root cause. At low frequency, the voltage noise across the PDN is usually due to the voltage noise from the VRM and so the first step in PDN design is selecting a VRM with low enough voltage noise under a suitable load current.

However, even with the world’s most stable VRM, voltage noise still exists on the pads of the die. This arises from the voltage drop across the impedance of the entire PDN from transient power currents through the gates on the die. Between the pads of the VRM and the pads on the die are all the interconnects associated with the PDN. We refer to this entire network as the PDN ecology.

As applied to the pads of the die, these interconnects contribute to an impedance profile. Figure 1.4 shows a typical example.

Figure 1.4

Figure 1.4 Example of an impedance profile of the entire PDN ecology, as applied to the pads of the die.

Any transient currents through this impedance profile generates voltage noise on the pads of the chip, independent of the VRM stability.

For example, Figure 1.5 shows the transient current spectrum drawn by the core power rail for a device when executing a specific microcode. Superimposed on the current spectrum is the impedance profile through which this current flows. The combination of the current amplitude and impedance at each frequency generates a voltage noise spectrum. This noise spectrum, when viewed in the time domain, results in a transient voltage noise.

Figure 1.5

Figure 1.5 Left Side: PDN impedance profile and transient current spectrum result in acceptable voltage noise. Right Side: Slight change in current spectrum gives unacceptable voltage noise.

The left side of Figure 1.5 shows the transient current spectrum, PDN impedance profile, and resulting voltage noise on the power rail. This combination of current spectral peaks and impedance peaks results in acceptable noise. On the right is the same impedance profile, but with slightly different microcode algorithm driving the same gates at a slightly different frequency. A current spectral peak ended up overlapping a larger impedance peak and generating a rail voltage noise above the acceptable limit.

The actual voltage noise generated by the transient current through the impedance profile depends on the overlap of the current frequency components and the peaks in the impedance profile. If the voltage noise is below a specified level, PDN induced errors will not occur. If the microcode changes resulting current amplitude peaks and frequency component changes, their overlap with impedance peaks might create more voltage noise and product failure.

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