This chapter is from the book
This chapter is from the book
This chapter is from the book
1.5 Power Noise to Signal Coupling
When an I/O interfaces is switching, SSO noise is produced when rapid charging/discharging currents flow through the PDN. The power to the signal coupling can be attributed to two major mechanisms. First is the chip level SSO coupling and the second is the interconnect level SSO coupling.
1.5.1 SSO
SSO or SSN occurs in a system with multiple buffers nearby switching at the same time, as shown in Figure 1.7. Rapid current draws from the buffers leave instantaneous void of electrons in power and ground planes. The instantaneous formation of an electron void may be too fast in a high-speed channel for the electrons from the nearby capacitor to fill in, which shows up as noise in the PDN that should be kept as stable as possible. As a result of the PDN fluctuation, signals of the buffers in the vicinity are affected, so the simultaneous switching impacts not only the PDN but also signal outputs. In this process, inductance in the PDN contributes to the voltage variation of the PDN through Delta-I noise. The term Delta-I refers to the di/dt voltage drop due to the inductance. SSO noise can occur for both single ended and differential drivers [6, 7].
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Figure 1.7 Block diagram of multiple buffers switching simultaneously
1.5.2 Chip-Level SSO Coupling
The impact of supply on signaling is dependent on the driver type and the signaling schemes. The power noise at the driver is coupled to the signals at the chip level. SSO noise at the buffer power/ground nodes propagates in the package and the PCB. This noise depends on the impedance of the PDN at the chip level, which is influenced by various stages on the PDN, including on-chip capacitance and package inductance. The chip level power noise to the signal coupling is significant. This coupling is important for single-ended signaling and differential signaling. Chapter 5, "Frequency Domain Analysis," describes the PDN resonance behavior and the power to signal coupling in frequency domain. Chapter 6, "Time Domain Analysis," describes the on-chip power noise coupling and its impact on signal performance in the time domain both for single-ended and differential channels. The power noise coupling at the chip results in signaling impact such as jitter.
1.5.3 Interconnect Level SSO Coupling
There are various mechanisms of interconnect level SSO coupling. A PCB power and signal distribution network includes not only planar conductors but also vertical structures, such as vias. A via is a pad with plated hole for electrical connections between conductor traces on different layers. The flat power-ground plane pair becomes a parallel plate wave guide or parallel plate cavity with short dimension along z-axis, as shown in Figure 1.8. The figure shows the ground net vias that are orthogonal to the power and ground plane structure. When the multiple buffers are switching, the excitation applied to the power-ground plane generates dominant radial waves that propagate in between the two planar conductors, as shown in Figure 1.9. Here, higher order waves are usually small in magnitude. The radial waves picked up by structures that are orthogonal to the planar power-ground conductors become unwanted noise. The noise in the power/ground planar cavity is coupled to the power/ground vias as well as signal vias. If there is a signal trace in between the power and ground cavity, the power/ground noise is coupled to the trace.
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Figure 1.8 Pulse excitation of a power-ground plane pair with 1mm dielectric thickness
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Figure 1.9 Radial wave propagation in power-ground plane pair
Sockets, connectors, and adjacent signal/power vias, introduce electromagnetic coupling between PDN and signal nets. In high-speed channel, these vertical structures with adjacent power/ground nets, and signal nets become vulnerable to the unwanted parallel coupling. Crosstalk in sockets' vertical structures often becomes the source of coupling between the signal and power.
Figure 1.10 shows a digital I/O channel with two IC chips: one (MCH) mounted on a PCB and the other (DRAM) mounted on a daughter-card. For the multi-layered high-speed systems, as shown in the figure, Delta-I noise, or SSO generated by I/O buffer switching propagates in the power and ground planes and significantly couples to the interconnects through signal reference transition. The coupled noise can be amplified due to transmission line effect and can cause severe signal integrity problems. In Chapter 7, "Signal/Power Integrity Interactions," various case studies are presented that illustrate the interaction between power and signal integrity including the interconnect level coupling. Chapter 8, "Signal/Power Integrity Co-Analysis," addresses the combined power and signal integrity analysis. It is essential for combined modeling and simulation of signal and power integrity to understand how SSO noise is translated into receiver jitter. Radiated emissions may occur at edge of the printed circuit board (PCB) due to the power/ground noise. Stitching capacitors or vias help mitigate these risks, but the effectiveness of the stitching capacitors appear to deteriorate at speeds higher than a few hundreds MHz.
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Figure 1.10 Power/ground noise coupling to signal line in a multilayers link
These types of noise issues and faults are extremely difficult to diagnose and solve after the system is built or prototyped. Understanding and solving these problems before they occur can eliminate having to deal with them further into the project cycle and in turn cut down the development cycle and reduce the cost.
A signaling scheme impacts power integrity and signal integrity because of their coupling differences in various stages of channels. Designing a system with a tight margin necessitates exploring the impact of these signaling options. Generally, differential signaling offers better quality signal at all speeds than single-ended signaling if all the physical conditions are reasonable. Single-ended signaling is usually easier to implement; however, it is usually more susceptible to reference disturbance, SSO noise, or ground bounce. For single-ended signaling, the impact of power noise coupling at the interconnect level is higher than that for differential signaling. For differential signaling, with lines tightly coupled, common-mode noises affect both lines. Thus at the receiver, the difference between the two lines remains almost constant. Stray transient noise on the two lines will get canceled at the receiver, alleviating the impact due to interconnect level power noise coupling. Chapters 7 and 8 address the power noise coupling to the signal at the interconnect level for single-ended and differential channels. Chapter 9 describes the signal and power integrity measurement techniques, including power to signal coupling characterization.