- Chapter 3: Microprocessor Types and Specifications
- Pre-PC Microprocessor History
- Processor Specifications
- SMM (Power Management)
- Superscalar Execution
- MMX Technology
- SSE (Streaming SIMD Extensions)
- 3DNow and Enhanced 3DNow
- Dynamic Execution
- Dual Independent Bus (DIB) Architecture
- Processor Manufacturing
- PGA Chip Packagingx
- Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
- Processor Sockets and Slots
- Zero Insertion Force (ZIF) Sockets
- Processor Slots
- CPU Operating Voltages
- Heat and Cooling Problems
- Math Coprocessors (Floating-Point Units)
- Processor Bugs
- Processor Update Feature
- Processor Codenames
- Intel-Compatible Processors (AMD and Cyrix)
- P1 (086) First-Generation Processors
- P2 (286) Second-Generation Processors
- P3 (386) Third-Generation Processors
- P4 (486) Fourth-Generation Processors
- P5 (586) Fifth-Generation Processors
- Pseudo Fifth-Generation Processors
- Intel P6 (686) Sixth-Generation Processors
- Other Sixth-Generation Processors
- Itanium (P7/Merced) Seventh-Generation Processors
- Processor Upgrades
- Processor Troubleshooting Techniques
MMX technology was originally named for multimedia extensions, or matrix math extensions, depending on whom you ask. Intel officially states that it is actually not an abbreviation and stands for nothing other than the letters MMX (not being an abbreviation was apparently required so that the letters could be trademarked); however, the internal origins are probably one of the preceding. MMX technology was introduced in the later fifth-generation Pentium processors (see Figure 3.2) as a kind of add-on that improves video compression/decompression, image manipulation, encryption, and I/O processingall of which are used in a variety of today's software.
Figure 3.2 An Intel Pentium MMX chip shown from the top and bottom (exposing the die). Photograph used by permission of Intel Corporation.
MMX consists of two main processor architectural improvements. The first is very basic; all MMX chips have a larger internal L1 cache than their non-MMX counterparts. This improves the performance of any and all software running on the chip, regardless of whether it actually uses the MMX-specific instructions.
The other part of MMX is that it extends the processor instructions set with 57 new commands or instructions, as well as a new instruction capability called Single Instruction, Multiple Data (SIMD).
Modern multimedia and communication applications often use repetitive loops that, while occupying 10 percent or less of the overall application code, can account for up to 90 percent of the execution time. SIMD enables one instruction to perform the same function on multiple pieces of data, similar to a teacher telling an entire class to "sit down," rather than addressing each student one at a time. SIMD allows the chip to reduce processor-intensive loops common with video, audio, graphics, and animation.
Intel also added 57 new instructions specifically designed to manipulate and process video, audio, and graphical data more efficiently. These instructions are oriented to the highly parallel and often repetitive sequences often found in multimedia operations. Highly parallel refers to the fact that the same processing is done on many different data points, such as when modifying a graphic image. The main drawbacks to MMX were that it only worked on integer values and used the floating-point unit for processing, meaning that time was lost when a shift to floating-point operations was necessary. These drawbacks were corrected in the additions to MMX from Intel and AMD.
Intel licensed the MMX capabilities to competitors such as AMD and Cyrix, who were then able to upgrade their own Intel-compatible processors with MMX technology.