- Chapter 3: Microprocessor Types and Specifications
- Pre-PC Microprocessor History
- Processor Specifications
- SMM (Power Management)
- Superscalar Execution
- MMX Technology
- SSE (Streaming SIMD Extensions)
- 3DNow and Enhanced 3DNow
- Dynamic Execution
- Dual Independent Bus (DIB) Architecture
- Processor Manufacturing
- PGA Chip Packagingx
- Single Edge Contact (SEC) and Single Edge Processor (SEP) Packaging
- Processor Sockets and Slots
- Zero Insertion Force (ZIF) Sockets
- Processor Slots
- CPU Operating Voltages
- Heat and Cooling Problems
- Math Coprocessors (Floating-Point Units)
- Processor Bugs
- Processor Update Feature
- Processor Codenames
- Intel-Compatible Processors (AMD and Cyrix)
- P1 (086) First-Generation Processors
- P2 (286) Second-Generation Processors
- P3 (386) Third-Generation Processors
- P4 (486) Fourth-Generation Processors
- P5 (586) Fifth-Generation Processors
- Pseudo Fifth-Generation Processors
- Intel P6 (686) Sixth-Generation Processors
- Other Sixth-Generation Processors
- Itanium (P7/Merced) Seventh-Generation Processors
- Processor Upgrades
- Processor Troubleshooting Techniques
Dual Independent Bus (DIB) Architecture
The Dual Independent Bus (DIB) architecture was first implemented in the sixth-generation processors from Intel and AMD. DIB was created to improve processor bus bandwidth and performance. Having two (dual) independent data I/O buses enables the processor to access data from either of its buses simultaneously and in parallel, rather than in a singular sequential manner (as in a single-bus system). The second or backside bus in a processor with DIB is used for the L2 cache, allowing it to run at much greater speeds than if it were to share the main processor bus.
The DIB architecture is explained more fully in Chapter 4, "Motherboards and Buses." To see the typical Pentium II/III system architecture, see Figure 4.34.
Two buses make up the DIB architecture: the L2 cache bus and the processor-to-main-memory, or system, bus. The P6 class processors from the Pentium Pro to the Celeron, Pentium II/III, and Athlon/Duron processors can use both buses simultaneously, eliminating a bottleneck there. The Dual Independent Bus architecture enables the L2 cache of the 1GHz Pentium III or Athlon, for example, to run 15 times faster than the L2 cache of older Pentium and K6 processors. Because the backside or L2 cache bus is coupled to the speed of the processor core, as the frequency of processors increases, so will the speed of the L2 cache.
The key to implementing DIB was to move the L2 cache memory off of the motherboard and into the processor package. L1 cache has always been directly a part of the processor die, but L2 was larger and had to be external. By moving the L2 cache into the processor, the L2 cache could run at speeds more like the L1 cache, much faster than the motherboard or processor bus. To move the L2 cache into the processor initially, modifications had to be made to the CPU socket or slot. There are two slot-based and three socket-based solutions that fully support DIB: Slot 1 (Pentium II/III/Celeron), Slot A (Athlon), Socket 8 (Pentium Pro), Socket 370 (Pentium III/Celeron), and Socket A (Athlon/Duron).
DIB also allows the system bus to perform multiple simultaneous transactions (instead of singular sequential transactions), accelerating the flow of information within the system and boosting performance. Overall DIB architecture offers up to three times the bandwidth performance over a single-bus architecture processor.