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1.2 Prototyping: Interconnecting High-Speed Digital Signals

Traditionally the professional engineer strives to design high-performance digital and embedded systems within tight time-to-market constraints, cost limitations, and quality demands while managing manufacturability requirements. Alongside the traditional concerns, the key challenge facing today's designer is the task of maintaining signal integrity in a modern high-performance digital system. A contemporary example of the changing landscape of embedded system design is the support given to the SI engineer by device manufacturers that integrate some ingenious circuitry within their devices to minimize or circumvent a number of SI issues. A particular case in point is the interplay between the SI engineer and modern programmable logic device manufacturers. The inclusion of programmable pre-emphasis, deskewing, edge rate control, and equalization provides a range of solutions to a number of key SI concerns.

As system speeds increase and timing budgets decrease, there is less time for switching between logic levels. Consequently, digital signal edges become faster, which results in the need for rigorous design requirements if signal integrity is to be maintained. High-performance digital systems are prone to two fundamental sources of signal degradation:

  • Digital degradation that is timing-related, such as synchronization and setup and hold violations, which often generate metastability or race conditions that typically produce erratic system behavior
  • Analog degradation, such as indeterminate signal amplitudes, power supply and ground variations, glitches, signal overshoot, crosstalk, and unwanted noise, that generates a diversity of system malfunctions

Both of these phenomena typically have their origins in printed circuit board (PCB) design or signal termination, but there are a myriad of other causes. Not surprisingly, there is a high degree of interaction and interdependence among digital and analog signal integrity requirements. The analog aspects of digital system design tend to cause the most concern. High-speed signals transmitted along PCB tracks tend to suffer from high-frequency attenuation, which makes it difficult for a receiver to interpret the information. The effect is similar to a low-pass filter, which decreases a signal's high-frequency content.

The main causes of high frequency attenuation are PCB dielectric loss, which is a capacitive effect, and the skin effect, which limits the signal to the surface of a conductor. As the data rate increases or the edge rate becomes faster, the signal frequency increases, and the dielectric loss becomes the dominant factor in high-frequency attenuation. The effect of dielectric loss is proportional to frequency, whereas the skin effect is proportional to the square root of the frequency. The skin effect describes how high-frequency currents tend to travel on the surface of a conductor, rather than on the whole cross section of the conductor. This is caused by the conductor's self-inductance, which increases the inductive reactance with frequency, forcing the current to travel on the surface of the material. This reduces the effective conductive area of a PCB trace, increasing the trace's impedance, which causes the signal to be attenuated.

While other PCB anomalies such as poor termination can cause crosstalk and reflections, the problem of high-frequency signal loss is aggravated as signal frequencies increase and PCB tracts lengthen. For example, Figure 1-2 shows the particularly demanding case of a 40-inch backplane where high-frequency signals are transmitted through a PCB stripline that is constructed with FR4-type PCB material.

Figure 1-2

Figure 1-2 The particularly demanding case of a 40-inch backplane where the signals are transmitted through a PCB stripline that is constructed with FR4-type PCB material.

Figure 1-3 shows the dominant high-frequency dielectric loss effect in a 40-inch PCB stripline. The loss is caused by the capacitance formed by the trace and ground plane with a dielectric constructed with PCB-type FR4 materials. All PCB laminate materials have a specific dielectric constant, which will affect the impedance of the trace, especially at high frequencies, where the trace behaves as a transmission line. The value of a PCB dielectric constant is determined by comparing the capacitive effect of the PCB material to the capacitive effect of a conductive pair in a vacuum, where the vacuum has a dielectric constant of 1. In Figure 1-3, the FR4 material has a dielectric constant of about 4 to 4.7. A lower dielectric constant can allow a PCB to support a longer transmission line before the high-frequency losses become significant, but this is a simplification. Determining dielectric loss is a complex topic. Many materials are used as PCB laminates, and many have better propagation characteristics than FR4. However, the high-performance PCB becomes too expensive for large-volume, low-cost applications. Although the extensive length of the backplane used in this example has exaggerated the loss effects, Figure 1-3 clearly shows how the dielectric loss is directly proportional to an increase in signal frequency. The skin effect is somewhat constant at –10 dB throughout the frequency range 5 GHz to 10 GHz. Lossless transmission lines are a bit of a misnomer because they consider only impedance and timing. Attenuation is considered in a second-level approximation of the line.

Figure 1-3

Figure 1-3 The dominant high-frequency dielectric loss effect in a 40-inch PCB stripline.

Both dielectric loss and skin effect can cause problems with intersymbol interference (ISI). The attenuation effectively prevents the signal from reaching its full amplitude within the required duration or its symbol time. As a result, the signal symbol, such as logic 1 or logic 0, spreads into the following symbol, mixing the symbols. The effect is pattern-dependent and is known as pattern-dependent jitter (PDJ) or data-dependent jitter (DDJ). If a string of data remains at the same level, such as a string of logic 0s, the energy in the signal has time to reach its peak, allowing the data to be transmitted and received correctly. However, for a quick switching signal, with alternating logic 1s and 0s, full signal strength is not reached within each symbol period. This causes the symbols to merge and the system to malfunction.

To maintain signal integrity in a modern digital system, differential signals and integrated signal processing functions within device drivers and receivers are becoming more common. Nonetheless, differential signals demand that designers pay special attention to PCB layout. Poorly designed differential traces and terminations can cause many of the signal integrity problems associated with conventional single-ended systems. Also, an intimate knowledge of signal pre-emphasis and equalization is necessary, because incorrectly applied pre-emphasis in effect generates unwanted overshoot, crosstalk, and noise.

1.2.1 The Effects of Increasing the Drive Signal

The simple solution to overcoming signal loss, or attenuation, is to increase the signal strength to overcome the attenuation. Unfortunately, increasing the signal strengths does not solve the problem of selective loss of high frequencies, or high-frequency roll-off. Also, the PDJ would deteriorate, because each symbol would be unable to achieve its full strength within its allotted time slot. Also, as a result of the increased signal level, each signal symbol will probably spread even further into the next symbol. Increasing the signal strength also affects the noise in the system, because noise increases proportionally with the increase in signal strength. What's more, the overall power consumption of the logic driver, or transceiver, also increases as the driver buffer increases the amount of current flowing into the PCB trace. Consequently, a simple increase in signal strength is not a solution to either the dielectric or skin-effect losses. In addition, increasing the signal strength may in fact make the situation worse.

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