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1.4 Components of a PDN

The elements of the PDN are shown in Figure 1-15 [8]; they include the chip-level power distribution with thin-oxide decoupling capacitors; the package-level power distribution with planes and mid-frequency decoupling capacitors; and the board-level power distribution with planes, low-frequency decoupling capacitors, and VRM. The frequency ranges covered by these elements are also shown in the figure: the power distribution operates at a higher frequency as the proximity to the active devices decreases because of the parasitic inductance and resistance of the interconnections between the active circuitry and the various elements of the PDN. These parasitic effects are explained in the next section.

Figure 1-15

Figure 1-15 Components of a PDN. By permission from M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system on package: status and challenges,” IEEE Transactions onAdvanced Packaging, vol. 27, no. 2, pp. 286–300, May 2004, © 2004 IEEE.

1.4.1 Voltage Regulator

Computer systems require multiple DC voltages to operate. These voltages have to be well regulated and should be able to supply the required current over a range of frequencies. The trend of increasing power and lowering supply voltage requires designers to move AC–DC and DC–DC converters closer to the electronics they feed [8]. A representative class of low-voltage high-current application is the core supply of central processing units (CPUs), digital signal processors (DSPs), and large switching chips. The voltage required may be in the 0.8 V to 2.5 V range, with the current in excess of 100 A for the largest devices. Since the core voltage is often unique and may be required only by the particular device, the DC–DC converters usually feed only one load and hence are also called point-of-load (POL) converters.

Besides the large current requirements, modern electronic circuits contain elements with several different supply voltages. Legacy 5-V and 3.3-V logic devices are still common, but newer devices often require 2.5 V, 1.8 V, 1.5 V, or even lower supply voltage. The pressing need for optimizing device speed while minimizing current consumption leaves little room to combine supply rails with similar but not exactly the same nominal voltage. The solution is therefore to place several DC–DC converters on the board to create the different supply voltages. The topology of these DC–DC converters is determined by two major system constraints: (1) most of the supply voltages are lower than the voltage of the primary source to the board (output of AC–DC converter or battery), so these converters usually have to step down the voltage; and (2) isolation is very seldom required in these converters. In AC-powered systems, the isolation can be easily provided in the AC–DC converters.

Because of these constraints, the single-phase, nonisolated buck converter is the most widely used DC–DC converter topology today, though for high-current applications, multiphase converters are also becoming popular. In a few applications, step-up boost converters and polarity-reversing buck-boost converters are also used.

1.4.1.1 Operating Principle

The VRM converts one DC voltage to another [9]. It has a reference voltage and a feedback loop. It senses the voltage near the load and adjusts the output current to regulate the voltage at the load. The bandwidth of the regulation loop is usually between one and several hundred kilohertz. At frequencies above the loop bandwidth, the VRM becomes high impedance, and therefore the voltage is no longer well regulated.

1.4.1.2 Four-Element Model

A four-element linear model for a VRM as described in [9] is explained in this section. Figure 1-16(a) is a simplified block diagram for a buck-switching regulator, commonly found in VRMs. At the left of the figure is an input voltage, assumed to be relatively constant. The function of inductor L1 is to store up energy when switch S1 is closed, and deliver current to the load. If L1 has more current than the load is demanding, S1 opens and S2 closes. Current continues to flow to the load, but in an ever-diminishing amount until S2 opens and S1 closes again. There is an amplifier A with frequency compensation that senses the load voltage with respect to a reference voltage. When the load voltage is too low, it causes the switches and inductor to ramp up the current. When the load voltage is too high, it causes the switches and inductor to ramp down the current. The inductor current is integrated in C1, which smooths the voltage. C1 has an ESR. The buck regulator is nonlinear because switches open and close as a function of time. Figure 1-16(b) shows the linearized model of the VRM consisting of an ideal voltage source and four passive elements. In the linear model, R0 is the value of the resistor between the VRM sense point and the actual load and is usually only a few milliohms. L_out represents the output inductance of the VRM. It may be the inductance of cables that connect the VRM to a system board or it may be the inductance of pins that connect a VRM to a module (about 200 and 4 nH, respectively). The maximum effective frequency for the VRM is determined by L_out. R_flat represents the ESR (explained in the next section) of the capacitor associated with the VRM. Generally, the capacitor determines the output impedance of the VRM at frequencies beyond the response time of the loop. The ideal voltage source has the value of the power supply voltage. The value of L_slew is chosen so that current will be ramped up in the linear model in about the same time that it is ramped up in a real VRM. It is calculated from the equation V = LdI/dt. In the equation, V is the amount of voltage droop or spike that can be accepted (say 5% of 1.8 V). The maximum transient current is used for dI. The total amount of time for the VRM to ramp this transient current either up or down is used for dt. As described in [7], typical model values for a VRM are R0 = 1 mW, L_out = 4 nH, R_flat = 30 mW, and L_slew = 67.5 nH.

Figure 1-16

Figure 1-16 (a) Diagram of buck-switching regulator. (b) Four-element model. By permission from L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284–291, Aug. 1999, © 1999 IEEE.

1.4.1.3 Design Challenges

The challenges for the DC–DC converters are multifold [8]. As a first challenge, the converters have to feed the low-voltage load with reasonable efficiency over a widely varying load-current range, which often requires synchronous rectification to keep losses low. Since the POL converters have to be placed close to the load, which will eventually dissipate the full output power, increasing the efficiency of the POL converter barely reduces the total power dissipation. However, higher converter efficiency can result in a smaller converter volume, which is usually the driving factor. Depending on the size and cost of the converter, their efficiencies are in the 85% to 95% range.

A second challenge is to optimize the converter's control loop to provide sufficiently low output transient ripple against the varying load current. Especially in the case of cascaded DC–DC converters, where the converter's input may have little transient filtering, the upstream converter's output has to deal with large current fluctuations. For example, a POL converter with 1.0-V output voltage and 30-A maximum current rating with a maximum of 60 mVpp load transient noise (excluding switching ripple) requires an output impedance below 2 mW (including the capacitors) (Z = 60 mV/30 A = 2 mW). At DC, providing low output resistance is relatively easy. With increasing frequency, however, the dropping loop gain creates an increasing output impedance of the converter. For guaranteeing unconditional stability against the unknown load impedance, some converters have very low bandwidth. If the converter's output impedance, for instance, exceeds the required 2 mW at 1 kHz, the on-board capacitors have to provide the impedance. At 1 kHz, 80,000 mF capacitance is required for providing a 2-mW capacitive reactance (Z = 1/[2p x 1000 x 80,000 x 10-6]). Figure 1-17 shows the small-signal output impedance of a POL converter at 1.5-V 20-A load, with a 680-mF external capacitor.

Figure 1-17

Figure 1-17 Measured small-signal output impedance of a Vin = 3.3 V, V = 1.5 V 20A POL converter with full DC load. By permission from M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system on package: status and challenges,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 286–300, May 2004, © 2004 IEEE.

A third challenge is to keep the conducted and radiated emissions of the converters under control. The converters are often placed very close to high-speed, low-swing digital interconnections and sensitive analog circuits. Since the peak AC current ripple is always higher in the converters than their DC output current, care must be taken to minimize the switching noise the converters introduce to nearby circuits. To reduce this interference, spread-spectrum converters have been introduced [9].

1.4.2 Bypass or Decoupling Capacitors

Switching transistor circuits requires current to charge the load. This current must be supplied by the PDN. When the VRM is unable to respond because of high output impedance, the current should be supplied by an alternative source for maintaining the voltage. In other words, when the output impedance of the VRM exceeds the desired impedance, then an alternative method is necessary to pull down the impedance. Bypass capacitors perform this function. Since capacitors store charge, they bypass the VRM and supply current to the switching circuits when there is a demand for it. These capacitors are also called decoupling capacitors because they decouple the VRM from the switching circuit. Bypass capacitors are classified as low-frequency, mid-frequency, and high-frequency capacitors depending on their operating range and their proximity to the transistor circuits.

1.4.2.1 Factors Affecting the Performance of Bypass Capacitors

The bypass capacitors are surface mount devices (SMDs) attached to pads on the PCB or package. The SMD capacitors have two terminals, one attached to the voltage plane and the other to the ground plane, as shown in Figure 1-18. When SMD capacitors supply charge (or current), the current leaves the voltage plane, travels through the voltage via, flows through the capacitor, and returns through the ground via and then to the ground plane, as shown in Figure 1-18. Given the current path, the factors affecting the capacitor performance are as follows:

  • Since the capacitor electrodes are made with conductors that have finite conductivity, they have resistance associated with them called as the equivalent series resistance (ESR) of the capacitor. Time-varying current flowing through the capacitor produces a magnetic field, resulting in inductance, called the equivalent series inductance (ESL) of the capacitor. The ESL interacts with the capacitance of the capacitor, causing it to resonate. The capacitors are capacitive below the resonant frequency and become inductive above the resonant frequency. The impedance of the capacitor can be written as

    Equation 1.18

    030equ01.jpg

    From equation (1-18), the capacitor resonates at a frequency

    Equation 1.19

    030equ02.jpg

    and at the resonance frequency, the impedance of the capacitor is Z = R. Hence, the minimum impedance achievable with the capacitor is R. At low frequencies, since the resistance and inductance contribution is low, the magnitude of the impedance (in dB) is given by

    Equation 1.20

    031equ01.jpg

    Hence, below the resonant frequency of the capacitor, the impedance has a negative slope of -20dB/decade. At higher frequencies, beyond the resonant frequency, the inductance contribution begins to exceed the resistance and capacitance contribution and the impedance therefore becomes

    Equation 1.21

    031equ02.jpg

    which has a positive slope of 20dB/decade (see Figure 1-19). To obtain low impedance for a given capacitance over a broad frequency range, both the ESR and ESL should be reduced so that the minimum impedance is small and the impedance beyond the resonant frequency is decreased as well.

  • The currents flowing through the vias in Figure 1-18 produce a time-varying magnetic field. For both the voltage and ground vias, the magnetic field surrounds the via in such a way that the flux passes through the loop formed by the voltage and ground currents. Such a magnetic flux results in inductance that can be reduced by reducing the loop area by placing the voltage and ground vias next to each other. Hence, the proximity of the voltage and ground pads that connect to the capacitor and the position of the vias with respect to the pad position become very critical; see Figure 1-20, which shows that the inductance can be halved by moving the pads and vias close to each other.
  • Using multiple via connections per pad can decrease the overall loop inductance [10]. With state-of-the-art low-inductance capacitor constructions, the inductance limitation becomes the external connections formed by pads, escape traces, and vias. This realization has given rise to capacitor case styles with multiple terminals. Today, the lowest inductance can be achieved with the various C4 or BGA capacitor packages [11]. When connected to the power and ground planes, the vertical via connections remain as the ultimate limiting factor for lowering inductance, which is discussed in Chapter 5.
  • The current from the capacitors must travel on the voltage plane to reach the transistor circuit and return through the ground plane back to the capacitor, thus forming a current loop. The voltage and ground planes therefore add additional inductance given by

    Equation 1.22

    032equ01.jpg

    where L is the per-unit-length (pul) inductance, d is the separation between the planes, and w is the plane width. The ability of the capacitor to supply current at higher frequencies can be enhanced by reducing the spacing between the voltage and the ground planes, thereby reducing the loop inductance.

  • Computer systems often have multiple capacitors of various types in parallel, which produces an antiresonance when the first capacitor becomes inductive while the second capacitor is in its capacitive region. The parallel circuit formed by the inductance and capacitance in parallel produces an impedance peak, which can be controlled by reducing the inductance (ESL) and resistance (ESR) of the capacitor. A similar effect can be seen when a decoupling capacitor is attached to a power and ground plane in its capacitive region, as explained by the following example.
Figure 1-18

Figure 1-18 Parasitics affecting performance of a bypass capacitor. By permission from L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitorselection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284–291, Aug. 1999, © 1999 IEEE.

Figure 1-19

Figure 1-19 Frequency response of a capacitor.

Figure 1-20

Figure 1-20 Inductance versus pad/via layout. By permission from L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284Ó291, Aug. 1999, © 1999 IEEE.

The characteristics of various capacitors used in a system are described in the next sections.

1.4.2.2 Bulk Decoupling Capacitors

Bulk decoupling capacitors maintain the PDN impedance at the required value beyond the VRM frequency and until the frequency at which mid-frequency capacitors become useful (typically from a few kilohertz to a few megahertz). Since bulk capacitors are connected to the VRM on one side, their values must be estimated in conjunction with the VRM output impedance.

Bulk capacitors typically have an ESR value in the range of 2 to 100 mW. Capacitors with a large ESR produce a flat impedance over a large frequency range, while a reduced ESR results in a sharper resonance, as the next example demonstrates.

An important parameter used to assess the usefulness of a capacitor is its quality factor Q. The quality factor of a capacitor is the ratio of its reactance to resistance and, for a series RLC circuit representation as in equation (1.18), can be written as

Equation 1.26

035equ01.jpg

In the inductive part of the frequency response, Q can be approximated as

Equation 1.27

035equ02.jpg

The Q factor should be minimized for a bypass capacitor either by reducing the ESL for a low ESR capacitor or by increasing the ESR for a high ESL capacitor (which is typically not preferred because it increases the impedance at resonance).

For wide frequency portions, the target impedance requirement may be flat, which corresponds to resistive impedance. Most available decoupling capacitors, however, have moderate or high Q factor, making it a challenge to create the flat impedance profile required. It has been shown that bypass capacitors with Q much less than 1 help to create flat impedance profiles with a minimum number of components [12], [13]. For fixed ESR and ESL, the Q of the capacitor varies inversely with capacitance. Therefore, creating smooth impedance transitions with large bulk capacitors, even with a low ESR, is an easier task. Providing a smooth impedance profile with multiple lower-valued, low-ESR ceramic capacitors is difficult and challenging, especially when the frequency dependency of capacitance, resistance, and inductance are taken into account. Reference [12] introduced the bypass quality factor (BQF) as a measure of effectiveness of the capacitor to cover a wide frequency range, where BQF = C/L (C: capacitance; L: inductance), indicating that a capacitor is more effective if the C/L ratio is higher.

For several hundred microfarad and higher capacitance values, tantalum, niobium, and various electrolytic capacitors have been used. The large capacitance dictates relatively large capacitor bodies, which in turn represent large inductance. Electrolytic capacitors in standard radial packages require a bottom seal in the can, creating few nanohenries of inductance. Tantalum and niobium capacitors are usually offered in brick case styles. The typical construction has a clip connection for the anode, introducing more than one nanohenry of inductance in spite of the smaller case style. Recently, low-inductance face-down constructions have been introduced with significantly lower inductance [14].

1.4.2.3 Mid-Frequency Decoupling Capacitors

The mid-frequency SMD capacitors are useful in the 10 to 100 MHz range and higher. These capacitors are primarily ceramic capacitors that come in several dielectric types (NPO, X7R, X5R, and Y5V) and several sizes (1206, 0805, 0603). NPO capacitors have the lowest ESR and best temperature and voltage properties but are only available up to a few nanofarads. X7R capacitors have reasonable voltage and temperature coefficients and are available from several nanofarads to several farads. X5R capacitors are similar to X7R but have reduced reliability and are being extended to 100 mF. Y5V dielectric capacitors are used to achieve high capacitance values but have very poor voltage and temperature characteristics [7].

The mid-frequency capacitors are much smaller than the bulk capacitors and therefore can be placed closer to the transistor circuit. Since the ceramic capacitors are smaller, they have lower ESR and ESL and lower capacitance than bulk capacitors, leading to a higher resonance frequency with a smaller impedance at resonance. Therefore, ceramic capacitors can be used at higher frequencies. Typical mid-frequency capacitors have capacitance in the range of 1 to 100 nF, ESR in the range of 10 to 100 mW, and ESL in the range of 0.5 to 1 nH.

Figure 1-22 shows the impedance versus frequency for several X7R and NPO ceramic decoupling capacitors. Notice that as the capacitance value decreases and the resonant frequency goes up, the impedance minimum does not dip down as low, since ESR is lower for high-valued capacitors. Capacitor effectiveness can be optimized by using low-inductance pads to increase the resonant frequency of a given capacitor, as shown in Figure 1-20 [7].

Figure 1-22

Figure 1-22 Frequency response of ceramic capacitors. By permission from L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Transactions on Advanced Packaging, vol. 22, no. 3, pp. 284–291, Aug. 1999, © 1999 IEEE.

More recently, embedded decoupling capacitors are being investigated for decoupling at higher frequencies. These capacitors are integrated within a package as an extra capacitor layer or between the voltage and ground planes. These capacitors are discussed in more detail in Chapter 5.

1.4.3 Package and Board Planes

Planes play a very important role at high frequencies by acting as high-frequency capacitors, serving as conduit for the transportation of current, and supporting the return currents of the signal lines referenced to it. Planes are large metal structures separated by a thin dielectric and are invariably used in all high-frequency packages and boards for power delivery and shielding. A plane pair is shown in Figure 1-23, which depicts the following:

  • Voltage and ground planes transport the current from the SMD capacitors to the switching circuits. The planes therefore control the inductance and delay from the capacitor to the switching circuit. At high frequencies much beyond the resonant frequency of the capacitor, the plane inductance dominates the impedance of the power distribution network.
  • The capacitance formed between the voltage and ground planes can be used to decouple the power supply at high frequencies and hence becomes a useful contributor.
  • Planes carry the return current of the signal lines, and hence the voltage fluctuations between the voltage and ground planes across the package and board are dictated by the plane behavior.
Figure 1-23

Figure 1-23 Role of planes and their parameters.

Package planes are effective for power distribution in the mid- to high-frequency range [8]. However, a major problem with power and ground planes is their behavior as electromagnetic resonant cavities, where dielectric constant of the insulator and the dimensions of the cavity determine the resonance frequency. When excited at the resonance frequency, the planes can become a significant source of noise in the package and board and also can act as a source of edge-radiated field emission if the impedance becomes large at these frequencies. Since the planes have unterminated edges on the four sides, any excitation of the planes creates an electromagnetic wave that stands in the cavity as time progresses. In other words, the wave travels back and forth in the region between the planes along the lateral direction, and over time a standing wave is generated. The standing waves in the cavity at resonance can produce significant coupling to neighboring circuits and signal lines [8]. It is important to note that since the plane separation d is much less than λ, the electromagnetic wave propagates only laterally, not vertically, between the planes. This limitation considerably reduces the complexity of the design and its analysis.

1.4.3.1 Power Plane Resonance

Figure 1-24 depicts the distribution of voltage fluctuations on the power and ground planes for an open-ended board of size a x b. As can be seen from the figure, the voltage distribution on the plane depends on the resonance mode (discussed in the next section), while the resonance frequency is determined by the mode number, dielectric constant of the insulator, and physical size of the planes. The resonance frequency of the planes is given by

Equation 1.28

039equ01.jpg

Figure 1-24

Figure 1-24 Voltage distribution and resonance frequencies generated by the power/ground plane cavity resonance on a open-ended PCB of size (a x b). Depending on the resonance mode, the voltage distribution and the resonance frequency vary. By permission from M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system on package: status and challenges,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 286–300, May 2004, © 2004 IEEE.

where the first mode in Figure 1-23 (assuming b > a) corresponds to a resonant frequency of

Equation 1.29

040equ01.jpg

In equations (1.28) and (1.29), m and e correspond to the permeability (typically that of air) and permittivity of the material between the planes. The distribution of the voltage across the plane depends on the source location.

As can be seen in Figure 1-24, at the resonant frequencies, the voltage distribution is maximum and minimum at certain points on the planes. This variation in the voltage fluctuation across the plane is called plane bounce. Large voltage fluctuations on planes can cause significant coupling to signal lines referenced to it, which can propagate to quiet receiver circuits and can also cause electromagnetic emission from the edges that are unterminated.

1.4.3.2 Plane Impedance

Since planes are passive structures, they can be represented using transfer functions. The parameter that is often used to understand plane characteristics is the impedance. The impedance of any two-port circuit can be defined as

Equation 1.30

040equ02.jpg

where V and I are the voltage and current at the two ports, and Z is the impedance. Equation (1.30) can be extended to an arbitrary number of ports.

Consider Figure 1-23. It consists of two planes, with the top plane assigned the DC voltage V and the bottom plane assigned to the DC voltage zero or ground. At the far end (right corner), the bottom plane is connected to an ideal ground, meaning that this is the position where the voltage is kept constant at 0 V by connecting to ideal ground. A port consists of two points (or nodes). For each port, the first node is on the top plane and the second node is on the bottom plane located under the first node. The bottom nodes represent the reference points for each port so that a voltage can be measured between the voltage and ground nodes. Assuming I1 = 1-A current source is connected at port 1 between the voltage and ground nodes with zero current at port 2, then the measured voltage V1 at port 1 is the impedance Z11, while the measured voltage V2 at port 2 is the impedance Z21. The same procedure can be repeated by applying a 1-A current source at port 2 and leaving port 1 as an open circuit to compute Z12 and Z22. Impedances Z11 and Z22 are called as the self-impedances, while Z21 and Z12 are called as the transfer impedances. These impedances can be modeled and measured, and can be used to represent the behavior of the planes. Since impedances are circuit quantities, they can be used in some circuit simulators to capture the behavior of planes.

1.4.3.3 Practical Considerations

Because the size of the package is smaller than the board (dimension a or b), the plane resonance frequencies of the board appear at a lower frequency than the package. In reality, package and board planes are connected to each other using solder balls and vias, and they can contain slits and cut-outs, resulting in a complicated behavior of the PDN. In addition, when numerous decoupling capacitors are connected to a power or ground plane cavity through the power or ground vias, the resonance frequency and the associated field distribution change because of the change in the effective capacitance and inductance of the plane cavity. The degree of the field distribution change and the resonance frequency shift depends on the capacitance and ESL of the decoupling capacitors and vias. Furthermore, the field distribution and the resonance frequencies can be slightly modified by the die attachment onto the package substrate.

At the plane antiresonance frequency, the power distribution impedance reaches its highest value, with the maximum value dictated by the losses in the structure. The loss includes radiation loss, conductor loss, dielectric loss, and losses associated with any components mounted on the package or board. The loss lowers the quality factor at resonance and hence reduces the noise [15]. In general, radiation and dielectric loss do not provide enough damping to completely eliminate resonances. Conductor loss can damp the resonance between power and ground planes when thin dielectrics are used [15].

At the resonance frequencies of the power and ground planes, the self-impedance and transfer impedance magnitudes may be large enough to create signal-integrity and electromagnetic interference (EMI) problems. The resonance can be suppressed in several ways. It has been shown that dielectric thickness below 10 mm between the power and ground planes forces a large part of the electromagnetic field to travel in the conductor rather than in the dielectric, thus effectively suppressing the plane resonance through conductive loss [16]. Lossy dielectric layers have also been proposed [17], though their potential impact on signals has not been published yet. For power-ground laminates with thickness greater than 50 mm, the plane resonance must be suppressed by other means. The smoothest impedance profile can be achieved with the lowest number of parts if the cumulative ESR of bypass capacitors equals the characteristic impedance of the planes, which requires either ceramic bypass capacitors with controlled ESR or low-inductance external resistors in series with low-ESR bypass capacitors [18].

1.4.4 On-Chip Power Distribution

High-performance on-chip power distribution networks [8] are constructed as multilayer grids, as shown in Figure 1-15. Since the on-chip power distribution is in close proximity to the switching circuits, it operates at frequencies above 1 GHz. Although on-chip power distribution is not the focus of this book, it is important to understand a few characteristics of this network, since it is one component in the system-level PDN.

Designing on-chip power distribution networks in high-performance microprocessors has become very challenging because of the continual scaling of CMOS process technology [19]. Each new technology generation results in a rapid increase in circuit densities and interconnect resistance, faster device switching speeds, and lower operating voltages. These trends lead to microprocessor designs with increased current densities and transition rates and reduced noise margins. The large currents and interconnect resistance cause large, resistive IR voltage drops, while the fast transition rates cause large inductive LdI/dt voltage drops in on-chip power distribution networks. Along with large voltage drops due to large dI/dt, electromigration (EM) is one of the critical interconnect failure mechanisms in ICs [20]. Electromigration, which is the flow of metal atoms under the influence of high current densities, causes increased resistance and opens in on-chip interconnects, causing further IR drops and potential reliability problems.

1.4.4.1 On-Chip Capacitors

On-chip power distribution systems for high-performance CMOS microprocessors must provide a low impedance path over a wide frequency range beyond 1 GHz. The impedance of the power distribution inductance increases with frequency according to Z = jwL, where w = 2pf, f is the frequency, and L is the inductance. On-chip decoupling capacitance is used as a local charge supply, which effectively lowers the power distribution impedance at high frequencies. Hence, high-frequency switching currents are "decoupled" from the inductance in the power distribution system, and switching noise is therefore reduced. The on-chip decoupling capacitance includes both the intrinsic decoupling capacitance (n-well and quiet circuit) and the add-on capacitance [21]. Intrinsic decoupling capacitance alone is not sufficient for acceptable noise suppression in high-performance microprocessor designs. Additional capacitance, often in the form of thin-oxide capacitors, which uses a thin-oxide layer between the n-well and polysilicon gate, is required.

1.4.4.2 Chip-Package Antiresonance

A major problem in combining the chip and package power distribution is chip-package antiresonance, which is explained in detail in a later section. The package inductance and chip decoupling capacitance form a parallel RLC circuit, which resonates at the frequency 043equ01.jpg , where L is the equivalent inductance of the package and C is the total nonswitching capacitance on-chip between voltage and ground. At this frequency, the power distribution seen by the circuits on the chip has a high impedance. If the chip operating frequency is near or at the chip-package resonant frequency, the noise voltage will be high. A large voltage fluctuation can build up over many cycles at this frequency when excited. In future generations of CMOS microprocessors, large amounts of on-chip decoupling capacitance, which shifts the chip-package resonant frequency well below the operating frequency, must be used to aggressively control switching noise [22].

A typical signature of AC differential noise at the center of a microprocessor operating at 3 GHz that consumes 150 W of power with a 1-V supply is shown in Figure 1-25 [8]. For this illustration, 210 nF of on-chip decoupling capacitance was used along with a low-inductance flip-chip package. The mid-frequency step response occurs when chip power changes abruptly from zero to the maximum power. The magnitude is decreased with on-chip decoupling capacitance. The oscillation frequency is the chip-package LC resonance. The mid-frequency noise is eventually damped, resulting in a residual high-frequency AC noise in the steady state. This steady-state response is due to the periodic switching of the microprocessor. The high-frequency steady-state noise rides on a DC offset, which is the IR drop caused by the chip power distribution resistance.

Figure 1-25

Figure 1-25 On-chip AC differential noise. By permission from M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system on package: status and challenges,” IEEE Transactions on Advanced Packaging, vol. 27, no. 2, pp. 286–300, May 2004, © 2004 IEEE.

1.4.4.3 Design Challenges

In the past, CMOS active power, which is the power used to do useful work such as switching circuits, has been the main focus of power delivery and management. However, as CMOS scales to 90 nm and below, process-related device leakage current represents a significant passive power component. This passive power includes many sources of device leakage current, such as junction leakage, gate-induced drain leakage, subthreshold channel currents, gate-insulator tunnel currents, and leakages due to defects [23], [24], [25], [26]. Two of these leakage currents, the gate-insulator tunnel current and the subthreshold channel current, are major problems with the scaling of technology. Beyond the 90 nm technology node, more than 50% of the total power can be attributed to leakage, which represents wasted power since no useful work is done.

Gate leakage current can be reduced by using high-K dielectric materials instead of silicon dioxide as the gate dielectric. The subthreshold component of power remains one of the most fundamental challenges as it equals the active component near the 65-nm technology node. This passive power component places a further strain on the on-chip power distribution system because it erodes the DC IR drop noise budget and compounds the electromigration problem.

On-chip voltage islands (logic and memory regions on the chip supplied through separate, dedicated power feeds) is becoming a design approach for managing the active and passive power problems for high-performance designs [26]. In such designs, the voltage level of an island is independent of other islands and is supplied from an off-chip source or on-chip embedded regulators. The design goal is to define regions of circuits within the chip that can be powered by a lower supply voltage while maintaining performance objectives and providing a reduction in active and passive power. Performance-limited critical paths are powered by the maximum voltage that the technology is optimized for, while paths with sufficient timing slack are powered with a lower supply. Hence, transistor libraries with multiple threshold voltages are used. Voltage islands in on-chip power distribution present challenges because isolation of decoupling capacitance reduces its effectiveness for nearby islands. Additional transients due to the activation and deactivation of islands must be managed. The distribution of multiple power supplies complicates the on-chip power grid design and introduces a potential wiring density loss.

1.4.5 PDN with Components

Figure 1-26 shows the complete PDN with the VRM, bypass capacitors, planes, and IC. The proximity of the various components to the IC can be inferred from Figure 1-26(a), where the VRM and bulk capacitors are farthest from the IC and the package planes and package capacitors are much closer. The frequency response of the individual components, their distance from the IC, and the parasitics between the component and the IC dictate the ability of any component to respond to the current demand from the IC. The circuit representation of the core PDN (no signal lines) is shown in Figure 1-26(b). The current flows from the capacitors or VRM through the planes in the package or PCB. The current always flows as a loop, returning to the source through the ground connection.

Figure 1-26

Figure 1-26 (a) Power delivery with components. (b) Circuit representation. (Courtesy of Professor Joungho Kim, KAIST, South Korea.)

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