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1.2 Simple Relationships for Power Delivery

In any IC, two kinds of circuits need to be powered: the core and I/O. The core consists of transistors that are contained within an IC and that communicate with each other. The I/O, on the other hand, has to communicate with other ICs through the package and motherboard. Because the wires connected to I/O circuits exit the IC, they are very noisy and often are isolated from the core circuits using a separate PDN, as shown in Figure 1-8, where both the core and I/O circuits during switching create voltage fluctuations across the power supply. In this section, simple relationships are derived for the voltage fluctuations on a power supply for both the core and I/O circuits.

Figure 1-8

Figure 1-8 Core and I/O circuits. (Courtesy of Professor Joungho Kim KAIST, South Korea.)

1.2.1 Core Circuits

A very simple circuit is shown for the core circuits in Figure 1-9(a), where the driver and receiver circuits are shown as 2 and 1, respectively. The PDN contains some resistance and inductance due to the parasitics of the interconnections in the network. The resistance is assumed to be negligible here. A simple equivalent circuit for Figure 1-9(a) is shown in Figure 1-9(b). In the simplified equivalent circuit, the switch represents the PMOS transistor that closes at time t = 0. The resistance R is the on-resistance of the transistor, and C is the input capacitance of receiver circuit 1 that needs to be charged. The total inductance of the voltage and ground paths is represented by a single inductance L.

Figure 1-9

Figure 1-9 (a) Core circuits switching. (b) Equivalent circuit. (c) Simplified equivalent circuit.

The goal of the core PDN is to ensure that sufficient charge is supplied to the switching circuit so that the capacitance can be charged to the required voltage. To minimize delay, the charge has to be supplied within a short time. The circuit in Figure 1-9(b) has two time constants: L/R and RC. The delay of the transistor circuit is defined by the RC delay. Since the L/R time constant should have minimum impact on the RC delay of the transistor, it is desired that [2]

Equation 1.2

011equ01.jpg

Under this assumption, the simplified equivalent circuit in Figure 1-9(c) can be used, where the voltage drop across the inductor can be obtained by solving equation (1.3),

Equation 1.3

012equ01.jpg

where the current is obtained by solving the differential equation:

Equation 1.4

012equ02.jpg

In equation (1.4), v(t) is an equivalent source voltage with rise time tr (that combines the switch and Vdd) given by

Equation 1.5

012equ03.jpg

The rise time is dictated by the speed of the switch. The maximum voltage across the inductor occurs at time t = tr and is given by

Equation 1.6

012equ04.jpg

1.2.2 I/O Circuits

I/O circuits, unlike core circuits, drive off-chip interconnections. With increase in frequency, the interconnections behave as transmission lines where the delay becomes important. The PDN used to drive an I/O circuit is shown in Figure 1-11(a): the transmission line has a characteristic impedance of Z0 and delay T. The far end of the transmission line is terminated with a resistor R = Z0. The inductance L represents the PDN loop inductance from the power supply to the chip terminals. As before, the transistor is represented using a switch with an on-resistance R, where R is much less than Z0 to allow for the maximum voltage to be launched on the transmission line, as shown in Figure 1-11(b).

Figure 1-11

Figure 1-11 (a) I/O circuit switching. (b) Simple equivalent circuit. (c) Voltage drop across inductor.

When the switch closes, the power supply inductance L acts as an open circuit and behaves as a short circuit at time t = infinity. As in the previous section, the voltage source and the switch can be combined and represented as a pulse with rise time tr. Since the far end of the transmission line is terminated in the characteristic impedance of the transmission line, there are no reflections. The maximum voltage drop across the inductor occurs at time t = tr and can be calculated as in the previous section by replacing R with Z0:

Equation 1.9

014equ01.jpg

Based on equation (1.9), a signal line with low Z0 (highly capacitive) will always result in a larger voltage drop across the inductor, assuming the inductance is fixed, as described later in this chapter. When tr is much greater than L/Z0, the maximum voltage drop across the inductor simplifies to

Equation 1.10

014equ02.jpg

When N parallel transmission lines of characteristic impedance Z0 are switched simultaneously, it is equivalent to switching a single transmission line of impedance Z0/N. Hence, the maximum voltage drop across the inductor can be obtained by replacing Z0 by Z0/N in equations (1.9) and (1.10).

1.2.3 Delay Due to SSN

The presence of the inductor increases the delay of the I/O circuit. The voltage at the input end of the transmission line for a pulse with rise time tr can be computed as

Equation 1.12

015equ02.jpg

and

Equation 1.13

015equ03.jpg

where

Equation 1.14

015equ04.jpg

and v(tr) = v(t = tr) from equation (1.12). A transistor circuit at the receiver requires a minimum voltage at its input to switch states. Let's assume that the minimum voltage required for this to happen at the driver output Vchip (input end of the transmission line) is 0.5 x Vdd. Equations (1.12) and (1.13) can be used to calculate the time required to reach 0.5 x Vdd and hence represent the delay incurred because of the power supply inductance. Equation (1.12) can be used when tr is greater than L/Z0, and equation (1.13) can be used when tr is less than L/Z0 to calculate a 50% delay. This delay does not include the transmission line delay and is valid for a matched load, as in Figure 1-11(b).

1.2.4 Timing and Voltage Margin Due to SSN

Timing and voltage margins are affected by crosstalk, process variation, SSN, reflection, and other effects. In this section, we address only the effect of SSN. SSN can affect the voltage margin because power supply noise can corrupt the voltage levels of the signal waveform. In the previous section, a relationship was derived between the SSN and delay: as the SSN increased for a larger number of switching drivers, the 50% delay increased as well. This delay manifests itself as jitter that affects the signal integrity of the waveform and therefore increases the timing error; see Figure 1-11(e). As an example, consider an 8-bit-wide bus. If all the bits transition simultaneously from 0 to 1 (00000000 to 11111111 for the bus), the maximum transient current from the power supply is drawn, resulting in maximum noise and hence maximum delay. If only the alternate bits transition (00000000 to 10101010), fewer drivers switch and therefore the noise (and delay) is lower than in the previous case. For a pseudorandom bit stream (PRBS), the number of switching drivers changes at random, resulting in random SSN. Therefore, the 50% delay associated with the rising edge changes with the bit pattern, resulting in an uncertainty in the position of the rising edge. This effect is called jitter, shown in Figure 1-11(e). Jitter results in a timing uncertainty whereby a longer time interval may be required to latch the data for all the bit patterns if the jitter is large. Hence, the goal in I/O signaling is to ensure the smallest timing error by controlling jitter, which is possible by reducing SSN in addition to other parameters. This ensures a suitable timing margin. In Chapter 5, this effect is described in more detail through an example.

1.2.5 Relationship between Capacitor and Current

As mentioned earlier, decoupling capacitors serve as charge reservoirs and provide current to the switching circuits. Let's assume that the power supply inductance is small such that equation (1.10) is valid. Consider a single 50-W driver, which requires a current of 0.1 A assuming Vdd = 5 V (DI = 5/50). Let's assume that a 100-nF capacitor is available to provide charge to the switching circuits during a time interval of 10 ns (tr) that keeps the power supply fluctuations to within 10% of Vdd. The current that can be supplied by the capacitor that maintains Dv to be 10% of Vdd is given by [6]

Equation 1.15

017equ01.jpg

Since a single driver requires 0.1 A to charge the interconnections, the 100-nF capacitor can provide the current to 50 I/O circuits over a period of 10 ns.

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