This chapter described the basic concepts in PDN design. The microprocessor and other ICs are sensitive to power supply fluctuations. An increase in the supply voltage causes reliability problems, while a decrease reduces the maximum operating frequency. By relating the impedance of the PDN and power supply noise, the network can be suitably designed in the frequency domain. By using the target impedance as a parameter for measuring the goodness of a PDN, the various components such as VRM, decoupling capacitors, vias, planes, and solder balls can be analyzed and optimized until the target impedance is met. The effect of the chip can also be included in the design process by representing it as either a lossless capacitor or a lossy capacitor. The relationship between impedance in the frequency domain and SSN in the time domain was also quantified in this chapter using simple models.