- A Sadly Familiar Tale
- Power On
- The Long Reach of Legacy Design
- Reflections on a Near Disaster
- Motivations to Develop a Simulation Strategy
- The Boundaries of Simulation Space
This chapter is from the book
This chapter is from the book
This chapter is from the book
The Long Reach of Legacy Design
Once again things seemed to be proceeding better than any engineer had a right to expect. Pre-production testing completed only a few days behind schedule. The team had closed all outstanding issues that arose during testing. Limited-availability hardware was in the hands of a few beta customers who were running their most strenuous loads. The contract manufacturer had finally optimized the solder profile, and board assemblies were starting to roll off the line with an acceptable defect level.
Unknown to the heroes of our story, another domino was falling at a distant semiconductor manufacturing plant. The board contained a 100 MHz synchronous DRAM interface that was several years old, and this interface used a memory address buffer that had been in production and was nearing end of life. The application required a relatively small amount of memory, and the original designer had opted to implement the interface directly on the board rather than using a DIMM. The current designer simply copied the schematics from a previous project. Nobody got too concerned because the interface had been functioning without trouble for so long. In the rush to market, long-term availability took a back seat.
The output impedance of the address buffer was a critical parameter in the DRAM interface. Each pin of the buffer had to drive four x8 DRAMs to make a 32-bit word—much less challenging than the eighteen loads typically found on an ECC DIMM. The 18-load application called for a low output impedance in the neighborhood of 15 Ω. The 4-load application needed 40 Ω. The same vendor had been supplying the contract manufacturer with address buffers for years but had recently fallen out of favor for cost reasons. Unfortunately, the new vendor used the same part number for the low- and high-impedance versions of the chip because none of their customers required them to specify output impedance on their datasheet. Seeing very little demand for the high-impedance buffers, they discontinued production and switched their entire output volume over to the 15 Ω buffer. Nobody knew the difference until the 100 MHz SDRAM interface on the Coyote boards started throwing parity errors during beta testing at a customer site. CEOs traded voicemails, and alarms started sounding again at Acme, Inc.
Anne had worked on a memory interface as a summer intern and was able to proceed through the failure analysis process with calmness and confidence. Her first order of business was to trace the history of the 100 MHz SDRAM interface back to its conception. She spoke with designers from the previous three projects that had used this interface. Each one had simply copied that schematics from their predecessor without performing any timing or signal analysis. At that point, the trail went cold. Nobody knew who the original designer actually was or if that person even was still an Acme employee. Anne decided to do her own timing budget using the datasheets and IBIS models available to her.
She pieced together the clock-to-output time from the buffer chip, the setup and hold times from the DRAM, and the clock chip pin-to-pin skew specification. Using the IBIS models she found on the Internet together with the datasheets, she ran a few quick behavioral simulations to determine how much the actual interconnect delay varied from the standard load listed in the component datasheet and documented her results using a simple spreadsheet timing budget (see Table 1.1). This was where things got interesting.
Table 1.1. 100 MHz SDRAM Address Timing Budget
|
Parameter |
Setup |
Hold |
Units |
|
Clock chip output skew |
0.5 |
-0.5 |
ns |
|
Address buffer clock-to-output delay |
3.0 |
1.0 |
ns |
|
Interconnect delay |
2.5 |
1.0 |
ns |
|
DRAM input setup time |
2.0 |
n/a |
ns |
|
DRAM input hold time |
n/a |
-1.0 |
ns |
|
TOTAL |
8.0 |
0.5 |
ns |
|
Clock period |
10.0 |
n/a |
ns |
|
OPERATING MARGIN |
2.0 |
0.5 |
ns |
The new buffer vendor supplied an IBIS model for only the 15 Ω buffer but did not distinguish between the two parts anywhere in the model. The old vendor supplied IBIS models for both parts, clearly labeling which was which. The IBIS models for the old vendor's parts passed the syntax checker, came with a quality rating, and ran the first time. The IBIS models for the new vendor were full of bugs and would not run. Technical support did not respond to her phone calls or emails, so she did the debugging herself.
Her simulation analysis of the 40 Ω buffer showed some gradually undulating reflections superimposed on an RC ramp. The 15 Ω buffer overdrove the net severely and caused a strong reflection that rang back into the threshold region of the DRAM receiver while the clock was sampling the address signal. A classic interaction of signal quality and timing: The interface met its timing constraints using the 40 Ω buffer but produced a setup time failure with the 15 Ω buffer. The solution to this problem was straightforward: Use the parts from the more reliable vendor and qualify a second vendor.