High-Speed Signaling: Jitter Modeling, Analysis, and Budgeting

Product Author Bios

Kyung Suk (Dan) Oh is Senior Principal Engineer at Rambus's Semiconductor Business Unit, responsible for signal integrity, power integrity analysis, and link budget analysis for mobile products. An IEEE senior member, he has twelve patents and applications, and has published 70+ papers. Xingchao (Chuck) Yuan  is engineering director in charge of a Rambus silicon team designing next generation graphics and main memory interfaces. His team is now researching graphics memory architecture to provide multi-terabytes of bandwidth without significant power consumption increases. His team's work led to the Rambus XDR memory architecture adopted in Sony's PlayStation 3.

New System-Level Techniques for Optimizing Signal/Power Integrity in High-Speed Interfaces--from Pioneering Innovators at Rambus, Stanford, Berkeley, and MIT

As data communication rates accelerate well into the multi-gigahertz range, ensuring signal integrity both on- and off-chip has become crucial. Signal integrity can no longer be addressed solely through improvements in package or board-level design: Diverse engineering teams must work together closely from the earliest design stages to identify the best system-level solutions. In High-Speed Signaling, several of the field’s most respected practitioners and researchers introduce cutting-edge modeling, simulation, and optimization techniques for meeting this challenge.

Edited by pioneering experts Drs. Dan Oh and Chuck Yuan, these contributors explain why noise and jitter are no longer separable, demonstrate how to model their increasingly complex interactions, and thoroughly introduce a new simulation methodology for predicting link-level performance with unprecedented accuracy.

The authors address signal integrity from architecture through high-volume production, thoroughly discussing design, implementation, and verification. Coverage includes

• New advances in passive-channel modeling, power-supply noise and jitter modeling, and system margin prediction
• Methodologies for balancing system voltage and timing budgets to improve system robustness in high-volume manufacturing
• Practical, stable formulae for converting key network parameters
• Improved solutions for difficult problems in the broadband modeling of interconnects
• Equalization techniques for optimizing channel performance
• Important new insights into the relationships between jitter and clocking topologies
• New on-chip measurement techniques for in-situ link performance testing
• Trends and future directions in signal integrity engineering

High-Speed Signaling thoroughly introduces new techniques pioneered at Rambus and other leading high-tech companies and universities: approaches that have never before been presented with this much practical detail. It will be invaluable to everyone concerned with signal integrity, including signal and power integrity engineers, high-speed I/O circuit designers, and system-level board design engineers.

Online Sample Chapter

Introduction to High-Speed Signaling

Table of Contents

Preface     viii
Chapter 1 Introduction     1
1.1 Signal Integrity Analysis Trends     4
1.2 Challenges of High-Speed Signal Integrity Design     8
1.3 Organization of This Book     9
References     11
Chapter 2 High-Speed Signaling Basics     13
2.1 I/O Signaling Basics and Components     13
2.2 Noise Sources     24
2.3 Jitter Basics and Decompositions     33
2.4 Summary     39
References     39
Part I Channel Modeling and Design     41
Chapter 3 Channel Modeling and Design Methodology     43
3.1 Channel Design Methodology     44
3.2 Channel Modeling Methodology     49
3.3 Modeling with Electromagnetic Field Solvers     52
3.4 Backplane Channel Modeling Example     54
3.5 Summary     63
References     64
Chapter 4 Network Parameters     65
4.1 Generalized Network Parameters for Multi-Conductor Systems     66
4.2 Preparing an Accurate S-Parameter Time-Domain Model     77
4.3 Passivity Conditions     85
4.4 Causality Conditions     89
4.5 Summary     98
References     101
Chapter 5 Transmission Lines     103
5.1 Transmission Line Theory     104
5.2 Forward and Backward Crosstalk    109
5.3 Time-Domain Simulation of Transmission Lines    115
5.4 Modeling Transmission Line from Measurements     121
5.5 On-Chip Wire Modeling    136
5.6 Comparison of On-Chip, Package, and PCB Traces     142
5.7 Summary     145
References     145
Part II Analyzing Link Performance    151
Chapter 6 Channel Voltage and Timing Budget    153
6.1 Timing Budget Equation and Components     155
6.2 Fibre Channel Dual-Dirac Model     156
6.3 Component-Level Timing Budget    160
6.4 Pitfalls of Timing Budget Equation     161
6.5 Voltage Budget Equations and Components    164
6.6 Summary     165
References     165
Chapter 7 Manufacturing Variation Modeling     167
7.1 Introduction to the Taguchi Method    168
7.2 DDR DRAM Command/Address Channel Example    179
7.3 Backplane Link Modeling Example    186
7.4 Summary     192
7.5 Appendix     193
References     196
Chapter 8 Link BER Modeling and Simulation    197
8.1 Historical Background and Chapter Organization    198
8.2 Statistical Link BER Modeling Framework    199
8.3 Intersymbol Interference Modeling     206
8.4 Transmitter and Receiver Jitter Modeling    210
8.5 Periodic Jitter Modeling     218
8.6 Summary    225
References    226
Chapter 9 Fast Time-Domain Channel Simulation Techniques     229
9.1 Fast Time-Domain Simulation Flow Overview     230
9.2 Fast System Simulation Techniques     232
9.3 Simultaneous Switching Noise Example     245
9.4 Comparison of Jitter Modeling Methods    246
9.5 Peak Distortion Analysis    248
9.6 Summary    253
References    253
Chapter 10 Clock Models in Link BER Analysis    257
10.1 Independent and Common Clock Jitter Models     258
10.2 Modeling Common Clocking Schemes     259
10.3 CDR Circuitry Modeling     268
10.4 Passive Channel JIF and Jitter Amplification     273
10.5 Summary     277
References     277
Part III Supply Noise and Jitter     279
Chapter 11 Overview of Power Integrity Engineering     281
11.1 PDN Design Goals and Supply Budget     282
11.2 Power Supply Budget Components     283
11.3 Deriving a Power Supply Budget     287
11.4 Supply Noise Analysis Methodology     290
11.5 Steps in Power Supply Noise Analysis     294
11.6 Summary     300
References     301
Chapter 12 SSN Modeling and Simulation     303
12.1 SSN Modeling Challenges     305
12.2 SI and PI Co-Simulation Methodology     310
12.3 Signal Current Loop and Supply Noise     321
12.4 Additional SSN Modeling Topics     325
12.5 Case Study: DDR2 SSN Analysis for Consumer Applications     330
12.6 Summary     336
References     337
Chapter 13 SSN Reduction Codes and Signaling     339
13.1 Data Bus Inversion Code     340
13.2 Pseudo Differential Signaling Based on 4b6b Code     346
13.3 Summary     357
References     357
Chapter 14 Supply Noise and Jitter Characterization     359
14.1 Importance of Supply Noise Induced Jitter     360
14.2 Overview of PSIJ Modeling Methodology     361
14.3 Noise and Jitter Simulation Methodology     364
14.4 Case Study     372
14.5 Summary     376
References     377
Chapter 15 Substrate Noise Induced Jitter     379
15.1 Introduction     380
15.2 Modeling Techniques     382
15.3 Measurement Techniques     391
15.4 Case Study     393
15.5 Summary     400
References     400
Part IV Advanced Topics     403
Chapter 16 On-Chip Link Measurement Techniques     405
16.1 Shmoo and BER Eye Diagram Measurements     407
16.2 Capturing Signal Waveforms     408
16.3 Link Performance Measurement and Correlation     411
16.4 On-Chip Supply Noise Measurement Techniques     412
16.5 Advanced Power Integrity Measurements     418
16.6 Summary     422
References     423
Chapter 17 Signal Conditioning     425
17.1 Single-Bit Response     426
17.2 Equalization Techniques     427
17.3 Equalization Adaptation Algorithms     433
17.4 CDR and Equalization Adaptation Interaction     442
17.5 ADC-Based Receive Equalization     445
17.6 Future of High-Speed Wireline Equalization     448
17.7 Summary     449
References     450
Chapter 18 Applications     455
18.1 XDR: High-Performance Differential Memory System     456
18.2 Mobile XDR: Low Power Differential Memory System     465
18.3 Main Memory Systems beyond DDR3     476
18.4 Future Signaling Systems     486
References     491
Index     495

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