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VLSI Design Methodology Development

VLSI Design Methodology Development

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Description

  • Copyright 2019
  • Edition: 1st
  • Book
  • ISBN-10: 0-13-565764-4
  • ISBN-13: 978-0-13-565764-5

Most traditional undergraduate microelectronics texts focus on detailed transistor modeling and behavior and fundamental circuit design techniques. However, the vast majority of working microelectronics engineers will design complex chips using existing circuit libraries. As they integrate existing intellectual property (IP), their design challenges will involve ensuring correct logical, physical and electrical properties, and preparing for reliable foundry fabrication. VLSI Design Methodology Development focuses on the design and analysis steps needed to perform these tasks and successfully complete a modern chip design. Writing from the perspective of a practicing engineer, leading microprocessor design authority Tom Dillinger explores each step of today’s chip design methodology in practical detail. This fresh and accessible tutorial helps engineers:

  • Understand modern VLSI design methodologies, IP models, steps, and options
  • Quickly get started with VLSI design, from floorplanning and physical integration to DFT, DFM, DFY, and hierarchical design decomposition
  • Perform key modeling tasks, including functional and behavioral modeling, design validation, and formal equivalency verification
  • Implement designs, including logic synthesis, placement, and routing
  • Analyze timing, noise, power, power rail voltage drop, electromigration reliability, and other electrical issues
  • Prepare for manufacturing release and bring-up, mastering ECOs, physical design verification, DFT Analysis, preparation for tapeout, post-silicon debug and characterization, and product qualification

Sample Content

Table of Contents

Topic I. Overview of VLSI Design Methodology
1. Introduction
2. VLSI Design Methodology
3. Hierarchical Design Decomposition

Topic II. Modeling
4. Modeling

Topic III. Design Validation
5. Characteristics of Functional Validation
6. Characteristics of Formal Equivalency Verification

Topic IV. Design Implementation
7. Logic Synthesis
8. Placement
9. Routing

Topic V. Electrical Analysis
10. Layout Parasitic Extraction and Electrical Modeling
11. Timing Analysis Section
12. Noise Analysis
13. Power Analysis
14. Power Rail Voltage Drop Analysis
15. Electromigration (EM) Reliability Analysis
16. Miscellaneous Electrical Analysis Requirements

Topic VI. Preparation for Manufacturing Release and Bring-up
17. ECOs
18. Physical Design Verification
19. Design-for-Testability Analysis
20. Preparation for Tapeout
21. Post-Silicon Debug and Characterization (Bring-up) and Product Qualification

Summary
Epilogue

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