The power of VHDL-without the complexity!
Want to leverage VHDL's remarkable power without bogging down in its notorious complexity? Get A VHDL Primer, Third Edition. This up-to-the-minute introduction to VHDL focuses on the features you need to get results-with extensive practical examples so you can start writing VHDL models immediately.
Written by Jayaram Bhasker, one of the world's leading VHDL course developers, this best-selling guide has been completely updated to reflect the popular IEEE STD_LOGIC_1164 package. With Bhasker's help, you'll master all these key VHDL techniques:
The book's extensive hardware modeling coverage includes modeling of regular structures, delays, conditional operations, state machines, Moore and Mealy FSMs, clock dividers and much more. You'll find new coverage of text I/O and test benches, as well as complete listings of the IEEE TD_LOGIC_1164 package. J. Bhasker has helped tens of thousands of professionals master VHDL. With A VHDL Primer, Third Edition, it's your turn to succeed.
What Is VHDL? History. Capabilities. Hardware Abstraction.
Basic Terminology. Entity Declaration. Architecture Body. Configuration Declaration. Package Declaration. Package Body. Model Analysis. Simulation.
Identifiers. Data Objects. Data Types. Operators.
Entity Declaration. Architecture Body. Process Statement. Variable Assignment Statement. Signal Assignment Statement. Wait Statement. If Statement. Case Statement. Null Statement. Loop Statement. Exit Statement. Next Statement. Assertion Statement. Report Statement. More on Signal Assignment Statement. Other Sequential Statements. Multiple Processes. Postponed Processes.
Concurrent Signal Assignment Statement. Concurrent versus Sequential Signal Assignment. Delta Delay Revisited. Multiple Drivers. Conditional Signal Assignment Statement. Selected Signal Assignment Statement. The UNAFFECTED Value. Block Statement. Concurrent Assertion Statement. Value of a Signal.
An Example. Component Declaration. Component Instantiation. Other Examples. Resolving Signal Values.
Generics. Why Configurations? Configuration Specification. Configuration Declaration. Default Rules. Conversion Functions. Direct Instantiation. Incremental Binding.
Subprograms. Subprogram Overloading. Operator Overloading. Signatures. Default Values for Parameters.
Package Declaration. Package Body. Design File. Design Libraries. Order of Analysis. Implicit Visibility. Explicit Visibility.
Entity Statements. Generate Statements. Aliases. Qualified Expressions. Type Conversions. Guarded Signals. Attributes. Aggregate Targets. More on Block Statements. Shared Variables. Groups. More on Ports.
Simulation. Writing a Test Bench. Converting Real and Integer to Time. Dumping Results into a Text File. Reading Vectors from a Text File. A Test Bench Example. Initializing a Memory. Variable File Names.
Modeling Entity Interfaces. Modeling Simple Elements. Different Styles of Modeling. Modeling Regular Structures. Modeling Delays. Modeling Conditional Operations. Modeling Synchronous Logic. State Machine Modeling. Interacting State Machines. Modeling a Moore FSM. Modeling a Mealy FSM. A Generic Priority Encoder. A Simplified Blackjack Program. A Clock Divider. A Generic Binary Multiplier. A Pulse Counter. A Barrel Shifter. Hierarchy in Design.
Reserved Words. Package STANDARD. Package TEXTIO.
Conventions. The Syntax.
The Package ATT_MVL.
VHDL-93 Features. Portability from VHDL-87.
Preface to Second Edition
Synthesis seems to be the driving force in making VHDL a popular hardware description language. As the number of synthesis users has grown, so has the popularity and usage of VHDL. Today, VHDL is an IEEE standard as well as an ANSI standard for describing digital designs.
According to IEEE rules, the language must be reballotted every five years to continue to exist as a standard. VHDL was first standardzed in 1987, and the standard was called IEEE Std 1076-1987. The first edition of this book was based on that version of the language. In 1992, the language was reballotted, and after much deliberation, in 1993, a new standard called IEEE Std 1076-1993 was developed. In this version, a number of new features have been added, syntax for certain constructs has been made more consistent, and many ambiguities in the earlier version have been resolved. An appendix in this book summarizes the changes.
This edition of the book describes VHDL as defined in IEEE Std 1076-1993. Models described in the earlier version of the language are strictly upward-compatible, except for very minor changes; these changes are listed in the appendix. This edition of the book has been expanded to include descriptions of the new features and the syntax improvements made to the language. The format of the first edition has been retained. Changes from the first edition are not identified separately. Several examples have also been added. In addition, a number of suggestions made by readers of the earlier edition have been incorporated.
I am greatly indebted to Paul Menchini for reviewing this revised edition of the book and providing valuable comments and thoughtful criticism, which have resulted in an improved edition of the book.