Shows the intimate connection between ASMs and implicit style Verilog.
Shows that complex digital and computer systems can be thought of as algorithms coded in implicit style Verilog — rather than the traditional gate, structural, or RTL approaches used by many designers.
Contains many practical examples of implicit style Verilog.
Describes pipelined systems as a natural extension of non-blocking assignment in implicit style Verilog.
Provides a unique full chapter on a superscalar processor.
Outlines the one to one mapping between ASM charts, implicit style Verilog, and one hot circuit diagrams.
Presents the Verilog Implicit to One hot (VITO) preprocessor — a novel way to automatically synthesize a one hot design from implicit style Verilog directly.
Verilog source code.
Links to software: VeriWell/Free; VerilogEASY; VITO; ARM (Advanced RISC Machines) HTML.
Verilog Digital Computer Design: Algorithms to Hardware
Shorten time to market with Verilog HDL
Real-world Verilog design, start-to-finish
The most productive way to design complex digital and computer systems is to understand them as algorithms and code them in implicit style Verilog, using Verilog's non-blocking assignment features. In this book, award-winning Verilog expert Mark Gord on Arnold shows how, introducing a top-down approach that leverages the ASM charts most digital designers are already familiar with. Throughout, you'll learn practical techniques that enable earlier debugging, automatic conversion of source code into hardware, and shorter time to market.
Arnold demonstrates a powerful new approach that automatically synthesizes a one-hot design directly from implicit style Verilog. He also introduces the elegant ARM instruction set as a way of exploring RISC design with implicit Verilog and ASMs. From start to finish, Verilog Digital Computer Design: Algorithms to Hardware is more than a great guide to Verilog: it's a primer on the enduring concepts of computer design that will apply no matter which tools you choose.
(NOTE: Chapters conclude with Conclusion, Further Reading, and Exercises.)
1. Why Verilog Computer Design?
What is computer design? A brief history of computer/digital technology. Translating algorithms into hardware. Hardware description languages. Typography. Assumed background.
What is an ASM chart? Pure behavioral example. Mixed examples. Pure structural example. Hierarchical design.
Simulation versus synthesis. Verilog versus VHDL. Role of test code. Behavioral features of Verilog. Structural features of Verilog. $time. Time control. Assignment with time control. Tasks and functions. Structural Verilog, modules and ports.
Pure behavioral examples. Mixed stage of the two-state division machine. Pure structural stage of the two state division machine. Hierarchical refinement of the controller.
Moore versus Mealy. Mealy version of the division machine. Translating Mealy ASMs into behavioral Verilog. Translating complex (goto) ASMs into behavioral Verilog. Translating conditional command signals into Verilog. Single-state Mealy ASMs.
Propagation delay. Factors that determine clock frequency. Example of netlist propagation delay. Abstracting propagation delay. Single cycle, multi-cycle and pipeline.
Moore ASM to one hot. Verilog to one hot. Mealy commands in a one hot machine. Moore command signals with Mealy<<=. Bottom testing loops with disable inside forever.
Introduction and history. Structure of the machine. Behavioral fetch/execute. Mixed fetch/execute. Memory hierarchy.
First attempt to pipeline. Example of independent instructions. Data dependencies. Data forwarding. Control dependencies: implementing JMP. Skip instructions in a pipeline. Our old friend: division. Multi-port memory. Pipelined PDP-8 architecture.
History of CISC versus RISC. The ARM. Princeton versus Harvard architecture. The register file. Three operands are faster than one. ARM subset. Multi-cycle implementation of the ARM subset. Pipelined implementation. Superscalar implementation. Comparison of childish division implementations.
Overview of synthesis. Verilog synthesis styles. Synthesizing enabled_register. Synthesizing a combinational adder. Synthesizing an implicit style bit serial adder. Switch debouncing and single pulsing. Explicit style switch debouncer. Putting it all together: structural synthesis. A bit serial PDP-8.
Memory reference instructions. Non-memory reference instructions. Group 1 microinstructions. Group 2 microinstructions.
Models of reality. Bus. Adder. Multiplexer. Other arithmetic units. Arithmetic logic unit. Comparator. Demux. Decoders. Encoders. Programmable devices. Conclusions. Further reading. Exercises.
D.1 System clock. Timing Diagrams. Synchronous Logic. Bus timing diagrams. The D-type register. Enabled D-type register. Up counter register. Up/down counter. Shift register. Unused inputs. Highly specialized registers. Further Reading. Exercises.
Switches. Single bit tri-state gate in structural Verilog. Bus drivers. Uses of tri-state. Further Reading. Exercises.
Prentice Hall. VeriWell Simulator. M4-128/64 demoboard. Wirewrap supplies. VerilogEASY. PLDesigner. VITO. Open Verilog International (OVI). Other Verilog and programmable logic vendors. PDP-8. ARM.
Efficient instruction set. Instruction set summary. Register Model.
Sequential logic. $strobe. Inertial versus transport delay. Sequence preservation. Further reading.
When I started teaching Verilog to electrical engineering and computer science seniors at the University of Wyoming, there were only two books and a handful of papers on the subject, in contrast to the overwhelming body of academic literature written about VHDL. Previously, VHDL had been unsuccessful in this course. For all its linguistic merits, VHDL is too complex for the first-time user. Verilog, on the other hand, is much more straightforward and allows the first-time user to focus on the design rather than on language details. Yet Verilog is powerful enough to describe very exotic designs, as illustrated in chapters 8-11.
As its subtitle indicates, this book emphasizes the algorithmic nature of digital computer design. This book uses the manual notation of Algorithmic State Machine (ASM) charts (chapter 2) as the master plan for designs. This book uses a top-down approach, which is based on the designerÕs faith that details can be ignored at the beginning of the design process, so that the designer's total effort can be to develop a correct algorithm.
Chapters 2-11 use the same elementary algorithm, referred to as the childish division algorithm, for many hardware and software examples. Because this algorithm is so simple, it allows the reader to focus on the Verilog and computer design topics being covered by each chapter. This book is unique in showing the correspondence of ASM charts to implicit style Verilog (chapters 3, 5 and 7). All chapters emphasize a feature of Verilog, known as non-blocking assignment or Register Transfer Notation (RTN), which is the main distinction between software and synchronous hardware. Except for chapter 6, this book ignores (abstracts away) propagation delay. Instead, the emphasis here is toward designs that are accurate on a clock cycle by clock cycle basis with non-blocking assignment. (Many existing Verilog books either provide too much propagation delay information or are so abstract as to be inaccurate on a clock cycle basis. Appendices C and D motivate the abstraction level used here.)
Chapter 4 gives a novel three-stage design process (behavioral, mixed, structural), which exercises the reader's understanding of many elementary features of Verilog. Chapter 7 explains an automated one hot preprocessor, known as VITO, that eliminates the need to go though this manual three-stage process.
This book defers the introduction of Mealy machines until chapter 5 because my experience has been that the complex interactions of decisions and non- blocking assignments in a Mealy machine are confusing to the first-time designer. Understanding chapter 5 is only necessary to understand chapters 9 and 10, appendix J and sections 7.4 and 11.6.
The goal is to emphasize a few enduring concepts of computer design, such as pipelined (chapters 6 and 9) and superscalar (chapter 10) approaches, and show that these concepts are a natural outgrowth of the non-blocking assignment. Chapter 6 uses AS M charts and implicit Verilog to describe pipelining of a special-purpose machine with only the material of chapter 4. Chapters 8, 9 and 11 use the classic PDP-8 as an illustration of the basic principles of a stored program computer and cache memory. Chapter 8 depends only on the ASM material of chapter 2. Chapter 9 requires an understanding of all preceding chapters, except chapter 7. The capstone of this book, chapter 10 (which depends on chapter 9), uses the elegant ARM instruction set to explore the RISC approach, again with the unique combination of ASMs, implicit Verilog and non-blocking assignment.
Chapters 3-6, 9 and 10 emphasize Verilog simulation as a tool for uncovering bugs in a design prior to fabrication. Test code (sometimes called a testbench) that simulates the operating environment for the machine is given with most designs. Chapter 10 introduces the concept of Verilog code coverage. Chapters 7 and 11, which are partially accessible to a reader who understands chapter 3, uses specific synthesis tools for programmable logic to illustrate general techniques that apply to most vendors' tools. Even in synthesis, simulation is an important part of the design flow. Chapter 11 will be much more meaningful after the reader has grasped chapters 1-9. The designs in chapter 11 have been tested and downloaded (www.phptr.com) into Vantis CPLDs using a tool available to readers of this book (appendix F), but these designs should also be usable with minor modifications for other chips, such as FPGAs.
Appendices A, B and G give background on the machine language examples used in chapters 8-11. Appendices C and D give the block diagram notation used in all chapters for combinational logic and sequential logic, respectively. Chapters 1-11 do not use tri-state bidirectional buses, but appendix E explains the Verilog coding of such buses.
This book touches upon several different areas, such as “computer design,” “state machine design,” “assembly language programming,” “computer organization,” “computer arithmetic,” “computer architecture,” “register transfer logic design,” “hardware/software trade-offs,” “VLSI design,” “parallel processing” and “programmable logic design.” I would ask the reader not to try to place this book into the pigeon hole of some narrow academic category. Rather, I would hope the reader will appreciate in all these digital and computer design topics the common thread which the ASM and Verilog notations highlight. This book just scratches the surface of computer design and of Verilog. Space limitations prevented inclusion of material on interfacing (other than section 11.6) and on multiprocessing. The examples of childish division, PDP-8 and ARM algorithms were chosen for their simplicity. Sections labeled “Further reading” at the end of most chapters indicate where an interested reader can find more advanced concepts and algorithms, as well as more sophisticated features of Verilog. Appendix F indicates postal and Web addresses for obtaining additional tools and resources. It is hoped that the simple examples of Verilog and ASMs in this book will enable the reader to proceed to these more advanced computer design concepts.
In places, this book states my opinions rather boldly. I respect readers who have differing interpretations and methodologies, but I would ask such readers to look past these distinctions to the unique and valuable approaches in this book that are not found elsewhere. I have sprinkled (somewhat biased) historical tidbits, primarily from the first quarter century of electronic computer design, to illustrate how enduring algorithms are, and how transient technology is. Languages are more algorithmic than they are technological. Just look at the endurance of the COBOL language for business software. Hardware description languages will no doubt change as the twenty-first century unfolds, but I suspect whatever they become, they will include something very much like contemporary implicit style Verilog.